PIC32CZ CA80/CA90 Family

39.7.12.2 TDF, (i.e. Data Float Time), Optimization Enabled (SMC M0DE.TDF M0DE = 1)

When the TDF_MODE of the SMC_MODE register is set to 1 (TDF data float optimization is enabled),the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert.

The following figure shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with:

NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)

NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)

TDF_CYCLES = 6; TDF_MODE= 1 (optimization enabled).

Figure 39-21. TDF, (i.e. Data Float Time), Optimization: No TDF Wait States are Inserted if the TDF Period is over when the Next Access Begins

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