37.13.1 USB Control Status Register Low for Endpoint0
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CSR0L |
| Offset: | 0x1012 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SERVICEDSETUPEND | SERVICEDRXPKTRDY | SENDSTALL | SETUPEND | DATAEND | SENTSTALL | TXPKTRDY | RXPKTRDY | ||
| Access | R/W/HC | R/W/HC | R/W/HC | R/W/HS | R/W/HS | R/HS | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – SERVICEDSETUPEND Clear SETUPEND Control bit
| Value | Description |
|---|---|
| 0 | Do not clear |
| 1 | Clear the SETUPEND bit in this register. This bit is automatically cleared. |
Bit 6 – SERVICEDRXPKTRDY Clear Control Bit
| Value | Description |
|---|---|
| 0 | Do not clear |
| 1 | Clear the RXPKTRDY bit in this register. This bit is automatically cleared. |
Bit 5 – SENDSTALL Send Stall Control Bit
| Value | Description |
|---|---|
| 0 | Do not send STALL handshake. |
| 1 | Terminate the current transaction and transmit a STALL handshake. This bit is automatically cleared. |
Bit 4 – SETUPEND Early Control Transaction End Status bit
This bit is cleared by writing a '1' to the SERVICEDSETUPEND bit
in this register.
| Value | Description |
|---|---|
| 0 | Normal operation |
| 1 | A control transaction ended before the DATAEND bit has been set. An interrupt will be generated and the FIFO flushed at this time. |
Bit 3 – DATAEND End of Data Control bit
The software sets this bit when:
- Setting TXPKTRDY for the last data packet
- Clearing RXPKTRDY after unloading the last data packet
- Setting TXPKTRDY for a zero length data packet
Hardware clears this bit.
Bit 2 – SENTSTALL STALL Sent Status bit
| Value | Description |
|---|---|
| 0 | Software clear of bit |
| 1 | STALL handshake has been transmitted |
Bit 1 – TXPKTRDY TX Packet Ready Control bit
| Value | Description |
|---|---|
| 0 | No data packet is ready for transmit |
| 1 | Data packet has been loaded into the FIFO. It is cleared automatically. |
Bit 0 – RXPKTRDY RX Packet Ready Status bit
This bit is cleared by setting the SERVICEDRXPKTRDY bit.
| Value | Description |
|---|---|
| 0 | No data packet has been received |
| 1 | Data packet has been received. Interrupt is generated (when enabled) when this bit is set. |