37.13.2 USB Control Status Register High for Endpoint0
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CSR0H |
| Offset: | 0x1013 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLSHFIFO | |||||||||
| Access | R/W/HC | ||||||||
| Reset | 0 |
Bit 0 – FLSHFIFO Flush FIFO Control bit
| Value | Description |
|---|---|
| 0 | No Flush operation |
| 1 | Flush
the next packet to be transmitted/read from the Endpoint 0 FIFO. The FIFO
pointer is reset and the TXPKTRDY/RXPKTRDY bit is cleared. Automatically
cleared when the operation completes. Should only be used when
TXPKTRDY/RXPKTRDY = 1. |