25.7.9.2 Linked-List with Cell Striding Example

Consider a simple video display scenario where a video frame buffer exists in memory at address location 0x2010_0000 as shown in the following figure.
Figure 25-10. Video Frame Buffer

The frame buffer is 640x480 pixels and a pixel is represented by a byte of data. The user would like to update the frame buffer with an animated sprite located at (50,240) or address 0x2012_5832 in the video frame buffer. The animated sprite frames are located in memory at 0x2002_0000. There are four frames in the animation and each sprite frame is 128x128 pixels (1 pixel/byte). The following figure shows each animation frame is stored in memory. The system display controller is setup to display the video frame buffer. The display controller is capable of generating a DMA request at the start of a vertical sync.

Figure 25-11. Sprite Frame

To animate the sprite, a channel on the DMA will be configured to update the video frame buffer at every vertical sync. On each vertical sync, the next frame of the animation is copied into the video frame buffer at location (50,240).

Software sets up a linked-list with four descriptors, one for each sprite frame. The linked-list is configured as a circular chain, so the fourth descriptor points back to the first descriptor as shown in the following figure. This will create a looped animation of the sprite.

Figure 25-12. Linked List with Cell Stride

For the Source Start Address, each descriptor points to a different frame of the animation.

Descriptor #1 (Sprite Frame 1):

BDSSA = 0x2002_0000,
        BDCFG.SSA=1

Descriptor #2 (Sprite Frame 2):

BDSSA = 0x2002_0080,
        BDCFG.SSA=1

Descriptor #3 (Sprite Frame 3):

BDSSA = 0x2002_0100,
        BDCFG.SSA=1

Descriptor #4 (Sprite Frame 4):

BDSSA = 0x2002_0180,
        BDCFG.SSA=1

The BCFG.ENABLE and BCFG.LLEN are both set to one for all four descriptors. Note, the only updates required for each successive image transfer is the Source Start Address, therefore this is the only optional information provided in each descriptor.

The DMA channel is configured as follows:

  • The address location for Descriptor #1 is loaded into the next descriptor register
    CHNXTk.NXT =
        &Descriptor #1
  • Destination Start Address is set to 0x2012_5832
    CHDSAk.DSA =
        0x2012_5832
  • The Block Transfer Size is set to the size of a single sprite frame, in this case 128x128 pixels = 16384 bytes
    CHXSIZk.BLKSZ =
        16384
  • The Cell Transfer Size is set to a 128 pixels = 128 bytes. The Source Cell Stride Size is set to 128x4 pixels = 512. This tells the DMA that each cell (128 pixels) is located 512 bytes apart. The Destination Cell Stride Size is set to 640 pixels = 640 bytes since that is the size of the video frame X dimension.
CHXSIZk.CSZ =
        128
CHSSTRDk.SSTRD =
        512-128
CHDSTRDk.DSTRD =
        640-128
  • Since this is a memory to memory data copy, the address sequence mode is set to Increment Address / Auto

CHCTRLBk.RAS=’b010

CHCTRLBk.WAS=’b010

  • The start trigger event is configured to use the vertical sync
CHCTRLBk.TRIG =
        Display Controller Vertical Sync
  • Since the entire sprite frame needs to be copied into the video frame buffer during the vertical sync, the user sets Cell Auto Start Enable of Ensuing Transfers
CHCTRLBk.CASTEN =
        1
  • All other channel features are disabled

Once the channel is configured, the user sets the CHCTRLAk.LLEN bit to 1.

At this point the DMA loads Descriptor #1 and updates the CHSSAk.SSA and CHNXTk.NXT registers before setting CHCTRLAk.ENABLE and CHCTRLAk.LLEN. On the next vertical sync trigger, the DMA transfers the sprite frame #1 into the video frame buffer. The DMA clears CHCTRLAk.ENABLE at the completion of the block transfer. Since LLEN=1, the next descriptor loads and SSA updates to the start of sprite frame #2, NXT is loaded with a pointer to Descriptor 3. Note, if a vertical sync trigger occurs while the DMA is loading a new descriptor, the trigger event is ignored since CHCTRLAk.ENABLE=0 at this time. The DMA configures CHCTRLAk.ENABLE=1 and LLEN=1 once the SFRs are configured. On the next vertical sync trigger, the DMA transfers sprite frame #2 into the video frame buffer. Again, on completion of the block transfers, the DMA loads the next descriptor. Each consecutive descriptor and block transfer are completed in a similar manner. Since the linked-list is circular, the animation loop continues until software sets CHCTRLAk.LLEN=0.