1.8.1.1 Transceiver Reference Clock Requirements
(Ask a Question)The following are the requirements for the transceiver reference clock:
- Ensure the following when differential clock input is provided to the
reference clock:
- ODT must be enabled for transceiver reference clock pins.
- Must be within the range of 20 MHz to 400 MHz.
- Must be within the tolerance range of I/O standards. The reference input buffer is provided and is expected to support these input standards directly without external components on the board. The reference I/O standards such as LVCMOS25, SSTL18, LVDS25, and HCSL25 are supported. For more information, see PolarFire Family Transceiver User Guide .
See the PCI Express Base specification Rev 2.1 for detailed PHY specifications. Also, see the PCIe Add-in Card Electro-Mechanical (CEM) specifications.