1.7 PCS Rate Switch Between 8b10b and 64b66b Mode for CPRI

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All CPRI protocol data rates are statically supported with the Libero Transceiver Configurator using either 8b10b or 64b66b modes. 8b10b supports CPRI rates 2, 3, 4, 5, 6, and 7 while 64b66b mode supports rates 7a, 8, and 9. In cases requiring dynamic switching, the user must take steps to accommodate the correct design intentions for switching the PCS mode between the data rates. This case requires a rate switch between the 8b10b and 64b66b modes.

8b10b ports are a superset of 64b66b ports. This implies that the user must plan the FPGA fabric design to interface with 8b10b ports of the XCVR and use the fabric to control the mode switching to the CPRI user IP as shown in the following figure.

Figure 1-59. PCS Rate Switch between 8b10b and 64b66b Mode

The following table lists the port crossover between the 8b10b and 64b66b modes provided by the XCVR PCS to the FPGA fabric.

Table 1-25. Port Crossover between the 8b10b and 64b66b Modes
Direction	8B10B Mode	64B6xB Mode
Input	TX_DISPFNC[15]	TX_ELEC_IDLE
Input	TX_DISPFNC[14]	TX_BYPASS_DATA
Input	TX_DISPFNC[13:12]	RESERVED_IN[1:0]
Input	TX_DISPFNC[11:8]	RESERVED_IN[5:2]
Input	TX_DISPFNC[7:6]	RESERVED_IN[7:6]
Input	TX_DISPFNC[5:2]	RESERVED_IN[11:8]
Input	TX_DISPFNC[1]	RESERVED_IN[12]
Input	TX_DISPFNC[0]	RESERVED_IN[13]
Input	TX_K[7:6]	RESERVED_IN[15:14]
Input	TX_K[5]	RESERVED_IN[16]
Input	TX_K[4]	TX_SOS
Input	TX_K[3:0]	TX_HDR[3:0]
Input	TX_DATA[63:33]	TX_DATA[63:33]
Input	TX_DATA[32:19]	TX_DATA[32:19]
Input	TX_DATA[18:17]	TX_DATA[18:17]
Input	TX_DATA[16]	TX_DATA[16]
Input	TX_DATA[15]	TX_DATA[15]
Input	TX_DATA[14]	TX_DATA[14]
Input	TX_DATA[13:12]	TX_DATA[13:12]
Input	TX_DATA[11:10]	TX_DATA[11:10]
Input	TX_DATA[9:8]	TX_DATA[9:8]
Input	TX_DATA[7:5]	TX_DATA[7:5]
Input	TX_DATA[4]	TX_DATA[4]
Input	TX_DATA[3]	TX_DATA[3]
Input	TX_DATA[2]	TX_DATA[2]
Input	TX_DATA[1]	TX_DATA[1]
Input	TX_DATA[0]	TX_DATA[0]
Output	RX_K[7]	RX_BYPASS_DATA
Output	RX_K[6:0]	RESERVED_OUT[6:0]
Output	RX_CODE_VIOLATION_7	RESERVED_OUT[13:7]
	RX_DISPARITY_ERROR_7
	RX_CODE_VIOLATION_6
	RX_DISPARITY_ERROR_6
	RX_CODE_VIOLATION_5
	RX_DISPARITY_ERROR_5
	RX_CODE_VIOLATION_4
Output	RX_DISPARITY_ERROR_4	RX_HDR_VAL
Output	RX_CODE_VIOLATION_3	STATUS_HI_BER
Output	RX_DISPARITY_ERROR_3	STATUS_LOCK
Output	RX_CODE_VIOLATION_2	RX_SOS
Output	RX_DISPARITY_ERROR_2	RX_DATA_VAL
Output	RX_CODE_VIOLATION_1	RX_HDR[3:0]
	RX_DISPARITY_ERROR_1
	RX_CODE_VIOLATION_0
	RX_DISPARITY_ERROR_0
Output	RX_DATA[63:51]	RX_DATA[63:51]
Output	RX_DATA[50:49]	RX_DATA[50:49]
Output	RX_DATA[48:9]	RX_DATA[48:9]
Output	RX_DATA[8:5]	RX_DATA[8:5]
Output	RX_DATA[4]	RX_DATA[4]
Output	RX_DATA[3:1]	RX_DATA[3:1]
Output	RX_DATA[0]	RX_DATA[0]
Input	TX_BIT_CLK⁴
Input	TX_PLL_LOCK⁴
Input	TX_PLL_REF_CLK⁴
Input	CTRL_CLK⁵
Input	CTRL_ARST_N⁵
Input	CALIB_REQ⁵
Input	LOS⁵
Input	CDR_REF_CLK
Output	CALIBRATING
Input	TX_WCLK⁶
Input	PCS_ARST_N
Input	PMA_ARST_N
Output	RX_VAL
Output	RX_READY
Output	RX_IDLE
Output	TX_CLK_STABLE
Output	RX_CLK_[R:G]
Output	TX_CLK_[R:G]
Input	RXD_P
Input	RXD_N
Output	TXD_P
Output	TXD_N

Note:

Port names in Libero has prefix lane#_ appended to name.
Refer to specific PCS port list tables for port description.
Ports prefixed by RESERVED for a specific mode is not used for the MODE.
Port is included in CLKS_FROM_TXPLL BIF.
Port is included with Enhanced Receiver Management (ERM).
TX_WCLK is included when Global (Shared) TX Clock is used.

The user control logic must accommodate switching transceiver control registers listed in the following table. This is typically by modifying the registers using the DRI to the transceiver from an APB within the design.

The following table outlines the affected registers that must be modified during rate switching.

Table 1-26. System Registers Affecting 8B10B and 64B6xB Data Paths
Register Page xls	Register Name	Field Name	Description	Required Value for 8B10B	Required Value for 64B6xB
pcslane	L8_R0	L8_TXENCSWAPSEL	Selects between 1000BASE-X/T and Fibre Channel octet-swapping modes.	Optional: 0=1000BASE-X/T, 1=Fibre Channel	Don’t-care
	L8_R0	L8_GEARMODE[1:0]	Sets data path width of FWF interfaces.	Must be consistent with clock selections for txfwf_rclk and rxfwf_wclk.	Don’t-care
	LOVR_R0	FAB_IFC_MODE[3:0]	Selects path through fabric and FWF overlay blocks.	Register changes the meanings of the epcs_tx_data and epcs_rx_data pins based on the setting of the pcslane LOVR_R0:PCSPMA_IFC_MODE[3:0] control register field. The PCSPMA_IFC_MODE is one-hot encoded as follows: 0b0100 == 8B10B mode	PCSPMA_IFC_MODE is one-hot encoded as follows 0b0010 == 64B6xB mode
	LOVR_R0	PCSPMA_IFC_MODE[3:0]	Selects lane mode for driving data into the SerDes serializer.
	LCLK_R0	LCLK_EPCS_RX_CLK_SEL [1:0]	Chooses which clock is sent to fabric on epcs_rx_clk port.	Usually this must be set to 2’d1 so that the frequency of the fabric is the same as the internal side of the FWF. However variations are possible if the use of the Rx FWF synchronous enable will be employed. See FWF description for further information.	2’d1
		LCLK_EPCS_TX_CLK_SEL [1:0]	Chooses which clock is sent to fabric on epcs_tx_clk port.		2’d1
pcslane	LCLK_R0	LCLK_PCS_RX_CLK_SEL [1:0]	Defines clock module’s source for pcs_rx_clk.	Must be set to 2’d3 for all applications using 8B10B function.	2’d3
		LCLK_PCS_TX_CLK_SEL [1:0]	Defines clock module’s source for pcs_rx_clk.		2’d3
		LCLK_RXFWF_WCLK_SEL [1:0]	Defines clock module’s source for rxfwf_wclk.	Must be consistent with L8_GEARMODE setting.	2’d2
		LCLK_TXFWF_RCLK_SEL [1:0]	Defines clock module’s source for txfwf_rclk.	Must be consistent with L8_GEARMODE setting.	2’d2
		LCLK_RXFWF_WCLK_PIPE	Defines whether Rx FWF is clocked by Tx side clocks or Rx side clocks.	Must be set to 1’d0 for 8B10B functionality.	1’d0
pcslane (continued)	LCLK_R1	LCLK_ENA_8B10B_RX_CLK	Instructs clock module to drive 8B10B pcs_rx_clk.	Must be set to 1’d1 for 8B10B operation.	1’d0
		LCLK_ENA_8B10B_RXFWF_WCLK	Instructs clock module to drive 8B10B rxfwf_wclk.
		LCLK_ENA_8B10B_TX_CLK	Instructs clock module to drive 8B10B pcs_tx_clk.
		LCLK_ENA_8B10B_TXFWF_WCLK	Instructs clock module to drive 8B10B txfwf_rclk.
		LCLK_ENA_64B6XB_RX_CLK	Instructs clock module to drive 64B6xB pcs_rx_clk.	1’d0	1’d1
		LCLK_ENA_64B6XB_RX_CLK_DIV2	Instructs clock module to drive 64B6xB pcs_rx_clk_div2.	1’d0	1’d1 for 64-bit fabric 1’d0 for 32-bit fabric
		LCLK_ENA_64B6XB_TX_CLK	Instructs clock module to drive 64B6xB pcs_tx_clk.	1’d0	1’d1
		LCLK_ENA_64B6XB_TX_CLK_DIV2	Instructs clock module to drive 64B6xB pcs_tx_clk_div2.	1’b0	1’b1 for 64-bit fabric 1’b0 for 32-bit fabric
pma_lane	DES_CLK_CTRL	DESMODE[2:0]	Selects parallel bus width of deserializer interface.	Must select the 40-bit wide bus mode for 8b10b functionality (3’d7).	Must select the 32-bit wide bus mode for 64B6xB functionality (3’d6).
	SER_CLK_CTRL	SERMODE[2:0]	Selects parallel bus width of serializer interface.
	DES_CDR_CTRL3	SLIP_DES_CDR_SEL	Selects source of CDR slip control.	Below setting is dependent on RX_SLIP_BIT enabled with the XCVR Configurator GUI. This has dependencies on the users fabric IP
		SLIP_DES_CDR_SEL	Selects source of CDR slip control.	Must be 1’d0 so that the fabric can control the symbol alignment.	Should be 1’d1 so that fabric cannot control the symbol alignment.
		SLIP_DES_CDR_EN	Optionally turns slip control OFF.	Must be set to 1’d1.	Must be set to 1’d0

Note: See respective PolarFire Device Register Map or PolarFire SoC Register Map for more information.