1.6 PMA and PCS Resets

The transceiver uses partitioned resets, one single wire for PMA_ARST_N and one for PCS_ARST_N to the PF_XCVR. Specifically, these two inputs can come from the FPGA fabric to reset the PMA and PCS portions of the transceiver. Both inputs assert the reset asynchronously and de-assertion is internally synchronized.

PMA_ARST_N reset always impacts both the Rx and Tx. This active LOW input resets all internal portions of the transceiver PMA including the serializer/deserializer, DFE, eye monitor, loopback FIFO, and internal analog circuits. The following figure shows the block diagram of PMA_ARST_N.

Control registers are available to selectively reset all components within the PMA and TXPLLs. These registers can be accessed through DRI (see Dynamic Reconfiguration Interface). For information about the register map, see respective PolarFire Device Register Map or PolarFire SoC Register Map.

PCS_ARST_N reset impacts either or both the receiver and the transmitter portion of PCS depending on transceiver mode (see Transceiver Modes). Resetting the Tx causes the serial link to be void of data toggling while internally restarting and the PCS transmit data path flushes out. Resetting the Rx causes the PCS active mode circuitry to be restarted. In 8b10b PCS mode, PCS_ARSTN is used to force the symbol alignment to restart when too many data errors are seen in the fabric logic.

PMA_ARSTN causes the RX clocks to stop. Users must not assert/de-assert the PMA_ARSTN reset through logic that is driven from the RX clocks as this would then create a lock-up situation where the PMA Reset is never de-asserted because the RX clock stops to toggle.

The functionality of the resets are register configured by the Libero software. See the respective PolarFire Device Register Map or PolarFire SoC Register Map for information about register maps. After Libero programming, these register controlled bits are written at power up prior to releasing the Tx PLL from reset. By doing this configuration during reset guarantees that the PCS Tx is reset without manual intervention.

In PMA Only XCVR configurations, the PCS_ARST_N can be tied to 1. This configuration assumes that the PCSLANE/LRST_R0/LRST_ULCKD_CDR_RESETS_PCS_RX register is set to 0x1 (default). This configuration resets the fly-wheel FIFOs within the PCS for PMA Only modes when the CDR automatically resets PCS Rx domain logic.

The Libero PCS_ARST_N configuration, Rx Only option, can only reset the Rx PCS when PCS_ARST_N signal falls; and self-reset the Tx PCS when the Tx PLL transitions from unlocked to locked. The Tx PLL lock is typically the last event which impacts the health of the clock going into the PCS from the PMA. However, if there is an application which requires a change to serializer post-divider or a change to the PLL that a Tx lane is using; these events cause a change in PCS clocking. These types of configuration changes must be carried out by first asserting the soft PCS Tx Reset system register, then changing the serializer configuration, and then de-asserting the soft PCS Tx Reset system register. This method assures the PCS plus its FWF sees a consistent clocking at the time when they are out of reset. Rate modifications must be done through DRI using a reset/modify/un-reset sequence and must be implemented by the user design. For such rate changes, the *ARST_N pins do not have to be used since soft resets are available through the DRI.

In 8b10b mode, the word aligner can only find a new pattern following a reset. Therefore, the Libero default is for PCS_ARST_N for Rx Only.

See Transceiver Modes for information about the impact of PMA and PCS resets.