1.3 Transceiver PCS Interface Modes

The transceiver PMA connects with the fabric using four PCS interface modes. PMA-PCS gearing is used in conjunction with the interface clock. The TX_CLK and RX_CLK frequency is equal to the FPGA interface based on the data rate/(PMA-PCS width × PCS gearing). The PCS interface instantiates the embedded transceiver and RTL blocks when the user customizes and generates the block. These 
pre-defined protocol interfaces provide data, control, and status signaling to the user logic in the FPGA fabric, including support for the following modes:

• 8b10b: encoding/decoding and word aligner.
• 64b6xb: 64b/66b or 64/67b encoding/decoding with gearbox logic.
• PIPE: a PHY interface for PCI Express (PIPE) supporting PCIe Gen2. Used with the embedded PCIe core or with the soft-IP hosted in the fabric. See PolarFire Family PCI Express User Guide for details about the embedded PCIe core solution. This interface is transparent with the PCIE (PCIESS) core.
• PMA only: direct access to the PMA without any encoding or decoding.