v2024.1

1 What's New
Information about what is new in Libero SoC Design Suite
2 Download Help
Information to help you download the Libero SoC Design Suite documentation
3 SmartHLS Compiler
Information about SmartHLS Compiler
4 Installation and Licensing
Information about Libero SoC software installation and licensing
5 Design Flow
Information about Design Flow
6 Block Flow
Information about Block Flow
7 SmartDesign
Information about SmartDesign
8 Netlist Viewer
Information about Netlist Viewer
9 I/O Editor
Information about I/O Editor
10 PDC Commands
Information about PDC commands for all families
11 Chip Planner
Information about Chip Planner
12 Timing Constraints Editor
Information about Timing Constraints Editor
13 SmartTime Static Timing Analyzer
Information about SmartTime Static Timing Analyzer
14 SmartPower
Information about SmartPower
15 Programming and Debugging
Information about Programming and Debugging
16 Macro Library
Information about Macro Library for SmartFusion2, IGLOO2 and PolarFire
17 Custom Flow
Information about Custom Flow
18 Design Separation Methodology
Information about Design Separation Methodology
19 Microchip Separation Verification Tool
Information about Microchip Separation Verification Tool
20 PolarFire SoC Microcontroller Subsystem (MSS)
Information about PolarFire SoC Microcontroller Subsystem (MSS)
21 Tcl Command Reference
Information about Tcl Command Reference
22 More Information
Additional information about other Microchip products
23 Technical Support
24 About Microchip
More information about Microchip

6.4.1 Peripheral and Embedded Hard Blocks

Various features of the architecture are located within the periphery but are not available within the FPGA array. These features can be incorporated within a block design but must be carefully enclosed to all the feature's I/Os within the block. Following are the list of features for PolarFire design:

DRI
APBM
SCB
ENFORCE
DEBUG
TVS
OSC_RC200MHZ
PF_SPI
SC_STATUS
UJTAG_SEC
SYS_SERVICES
VOLTAGEDETECT
OSC_RC2MHZ
INIT
TAMPER
PCIE
XCVR_PIPE_AXI0
XCVR_PIPE_AXI1

Note: While checking these interfaces in Chip Planner, flyline connections could converge at a single co-ordination. A large bus structure spread across an area is seen in the Chip Planner when the actual routing is viewed. If any I/O has an external name, off the chip, then it must be the same port name as in the top-level of the design.