22.1 SmartHLS Compiler

SmartHLS raises the FPGA design abstraction from traditional hardware description languages to C/C++ software, enabling shorter design time, easier verification and faster time to market for designs using our FPGAs.

In SmartHLS, you can implement your design in C++ software and verify the functionality with software tests. Next, the SmartHLS high-level synthesis software compiles the C++ program into functionality-equivalent Verilog hardware modules. SmartHLS can run co-simulation with ModelSim to verify cycle-accurate hardware behavior and confirm that the hardware functionality matches the software. SmartLHS can generate hardware IP cores that you can integrate into a larger system using SmartDesign. SmartHLS can also run Libero synthesis on the generated Verilog to determine the FPGA area and fMAX.

For more information, see Smart HLS Compiler.