10.1.3.4 set_location

This PDC command assigns the specified macro to a particular location on the chip.

set_location -inst_name <macro_inst_name> -fixed <true|false> -x <integer> -y <integer>

Note: This command may not honor placing globals to physical locations on the die. Instead of placing globals on die locations, let the Libero Design Suite decide where to place the global buffers.

Arguments

-inst_name: Specifies the instance name of the macro in the netlist to assign to a particular location on the chip.

-fixed <true | false>

Sets whether the location of this instance is fixed (that is, locked). Locked instances are not moved during layout. The default is YES.

The following table lists the acceptable values for this argument.

Table 10-24. -inst_name Values
Value	Description
True	The location of this instance is locked.
False	The location of this instance is unlocked.

-x -y: The x and y coordinates specify where to place the macro on the chip. Use the Chip Planner tool to determine the x and y coordinates of the location.

Exceptions

None

Example

This example assigns and locks the macro with the name mem_data_in\[57\] at the location x = 7, y = 2:

set_location -inst_name mem_data_in\[57\] -fixed true -x 7 -y 2

DDR3 Memory Placement

DDR3 memory must be placed in specific locations on the PolarFire chip to meet timing requirements. For DDR3 memory placement, the set_location command has the following syntax:

set_location -inst_name <hierarchical path to DDR instance> -location <edge>_<anchor>

-inst_name <hierarchical path to DDR instance>: Specifies the hierarchical path to the DDR instance.

-location <edge>_<anchor>: Specifies the edge_anchor location.

Example

set_location -inst_name {DDR3_TOP/DDR3_0}\ -location {NORTH_NE}

The maximum DDR width varies with the die/package combinations and the location they are placed in. See the following table for the correct location to place the DDR3 memory. The numbers in the table refer to the maximum DDR3 width.

Table 10-25. Locations for Placing DDR3 Memory
Die/Package	Location (Edge_Anchor} Edge={NORTH/SOUTH/WEST}, Anchor={NE/NW/SE/SW}
Die/Package	NORTH_NE	NORTH_NW	SOUTH_SE	SOUTH_SW	WEST_NW	WEST_SW
MPF200/FULLPKGE	16	16	Invalid Loc	40	64	40
MPF300/FCG1152	64	72	16	40	72	64
MPF300/FCG484	8	8	Invalid Loc	32	Invalid Loc	16
MPF300/FCVG484	16	16	Invalid Loc	40	16	16

PLL Placement

For PLL placement, the set_location command has the following syntax:

set_location -inst_name <hierarchical inst name> -location <PLL location>

-inst_name <hierarchical inst name>

Specifies the hierarchical instance name.

-location <PLL location>

Specifies the PLL location. Location can be one of the following:

PLL0_NW
PLL1_NW
PLL0_NE
PLL1_NE
PLL0_SW
PLL1_SW
PLL0_SE
PLL1_SE

For more information, see Placement Rules for PLLs and DLLs.

DLL Placement

For DLL placement, the set_location command has the following syntax:

set_location -inst_name <hierarchical inst name> -location <DLL location>

-inst_name <hierarchical inst name>

Specifies the hierarchical instance name.

-location <DLL location>

Specifies the DLL location. Location can be one of the following:

DLL0_NW
DLL1_NW
DLL0_NE
DLL1_NE
DLL0_SW
DLL1_SW
DLL0_SE
DLL1_SE

For more information, see Placement Rules for PLLs and DLLs.

TxPLL Placement

For TxPLL placement, the set_location command has the following syntax:

set_location -inst_name <hierarchical inst name> -location <TxPLL location>

-inst_name <hierarchical inst name>

Specifies the hierarchical instance name.

-location <TxPLL location>

Specifies the TxPLL location. Location can be one of the following:

Q2_TXPLL0
Q2_TXPLL_SSC
Q2_TXPLL1
Q0_TXPLL0
Q0_TXPLL_SSC
Q0_TXPLL1
Q1_TXPLL0
Q1_TXPLL_SSC
Q1_TXPLL1
Q3_TXPLL_SSC
Q3_TXPLL1

For more information, see Placement Rules for Transceivers.

Placement Rules for PLLs and DLLs

The following table lists the error messages that indicate non-compliance with placement rules for PLL and DLL.

Table 10-26. Error Messages
Error Code	Error Message	Description
PRPF_010	There can be a maximum of 6 PLL/DLL reference and/or fabric clocks coming driven by the FPGA fabric in the <NW\|SW\|NE\|SE> location.	There are four corners (NW, SW, NE, SE) that PLL and DLL instances can be placed in on each MPF300 or MPF200 FPGA device. You can place multiple PLL/DLL instances in each corner. However, for each corner, the total of PLL/DLL reference clocks and fabric clocks that the fabric drives must be six or less.
PRPF_011	There can be a maximum of 2 PLL/DLL reference clocks coming driven by the FPGA fabric in the <NW\|SW\|NE\|SE> location.	For each corner, only two PLL/DLL reference clocks can be driven by the fabric.

Placement Rules for RGMII, SGMII, and IOG CDR Interfaces

Placement rules must be adhered to for RGMII, SGMII, and IOG CDR interfaces. Non-compliance with these rules may result in the following errors.

Table 10-27. Error Messages
Error Code	Error Message	Description
PRPF_001	Port <port name> for Interface <inst name> must be placed before running Place-and-Route.	All PADs must be placed using the `set_io` command.
PRPF_002	Interface <inst name> has ports that must be assigned to the same physical lane. The current port assignment for this interface does not meet this requirement.	For the SGMII interface and IOG CDR, all RX_ and TX_ PADs must be placed in the same lane. For the RGMII interface, all RX [ ] PADs and the RXCLK PAD must be placed in the same lane.
PRPF_003	The current Interface <inst name> port assignment requires that pin <pin name (functional pin name)> is reserved. You must not assign any port to that package pin.	For the SGMII interface and IOG CDR, the `DQS_N` pin of the lane is reserved for internal use. It must be left unused.
PRPF_004	You must not assign <inst name> to any location. Use the set_io command to assign any interface port to package pins. This instance is automatically placed.	IOD instances with TRAINING/OVERLAY must not be placed. These are internal instances and will be handled by the tool.
PRPF_005	Port <port name> for Interface <inst name> must be assigned to <pin name (functional pin name)>.	For the RGMII interface, `RX_CLK` must be assigned to the DQS (P pad) of the lane.

Placement Rules for Transceivers

For PolarFire designs with the transceiver (XCVR) interface, some placement rules apply. Non-compliance with these rules may result in the following errors. For more information about rules for transceivers, see PolarFire Family Transceiver User Guide .

Table 10-28. Error Messages
Error Code	Error Message	Description
PRPF_007	TxPLL <inst name> must be placed before running Place-and-Route.	Transceiver Tx PLLs must be placed by the user with the `set_location` command before running Place-and-Route.
PRPF_008	Dedicated XCVR ports <port name>* must be placed before running Place-and-Route.	The transceiver interface has dedicated ports. These must be placed using the `set_io` command.
PRPF_009	Dedicated XCVR reference clock port <port name> must be placed before running Place -and-Route.	All transceiver reference clock PADs must be placed using the set_io command before running layout.
PRPF_008	Dedicated XCVR ports <port name>* must be placed before running Place & Route.	The transceiver interface has dedicated ports. These must be placed using the set_io command.
PRPF_009	Dedicated XCVR reference clock port <port name> must be placed before running Place & Route.	All transceiver reference clock PADs must be placed using the `set_io` command before running layout.
PRPF_009	Dedicated XCVR reference clock port <port name> must be placed before running Place & Route.	The transceiver interface has dedicated ports. These must be placed using the `set_io` command.