1.3 What’s New in SmartHLS 2025.1

Release Date: May 2025

Software Features and Enhancements

Upgraded Compilation Environment
  • The core compiler framework has been upgraded from Clang/LLVM 14.0.6 to 15.0.7.
  • The software simulation compiler has been upgraded from GNU GCC 5.4 to 8.5.
  • In SmartHLS 2024.2 and earlier, the C++ standard used for design compilation was preset to C++11. Now, it is customizable by setting the new CXX_STANDARD Makefile variable , with the default set to 14 (for C++14). For example, users can compile their designs in C++17 mode by adding CXX_STANDARD=17 to the HLS Makefile.
Improved Multiplication Synthesis
The process of multiplication splitting, which decomposes and maps wide multiplication operations to target Math blocks, has been improved. This improvement involves adopting a refined multiplication characterization method that ensures more accurate resource and performance estimates for all supported multiplication modes on the target device. This facilitates the derivation of improved circuitry.
To empower users to explore a wider range of solutions, a new set of constraint parameters has been introduced. These parameters allow for precise control over pipeline depth and resource utilization, streamlining the process for users.
  • The new ENABLE_MULTIPLY_SPLITTING parameter allows users to turn off the multiply splitting feature.
  • The new FORCED_MATH_BLOCK_PIPELINE_DEPTH parameter allows users to explicitly set the pipeline depth for Math blocks. This replaces the complicated automatic pipeline mode selection (achieved through ENABLE_AUTOMATIC_MULTIPLY_MODE_SETTING and MULTIPLY_SPLITTING_FULLY_PIPELINED in the previous release) and provides greater flexibility. Consequently, design constraints that previously used ENABLE_AUTOMATIC_MULTIPLY_MODE_SETTING or MULTIPLY_SPLITTING_FULLY_PIPELINED have to be ported to use FORCED_MATH_BLOCK_PIPELINE_DEPTH.
  • Specifying integer multiply latency using the set_operation_latency will no longer automatically disable the multiply splitting feature starting in this release.
Improved Pointer Casting Support
  • SmartHLS now supports type casting of pointers that point to arrays of primitive data types, whether passed as input arguments or declared locally within a function, provided that the alignment rules specified in the C/C++ standard are not violated. An example is shown below:
    void dut( uint8_t in_8[N] ) {
        uint8_t  local_8[N];
     
        uint32_t *pin8_32    = (uint32_t *)in_8;
        uint32_t *plocal8_32 = (uint32_t *)local_8;
    }
  • Support type casting between primitive data typed array/pointer and the size equivalent HLS arbitrary precision data typed array/pointer. For more information, see Libraries. An example is shown below:
    uint8_t          d_u8[N];
    hls::ap_uint<8>  *p_u8 = (hls::ap_uint<8> *)d_u8;
API Update in Streaming Library
  • full() should only be used in design code that generates output data to the corresponding FIFO.
  • empty() should only be used in design code that consumes input data from the corresponding FIFO.
  • To assist debugging in software simulation, a FIFO can now be identified by assigning a user-defined name using the new setName() API.
Improved HLS Pipeline Result Reports
  • The resource constraint report for designs utilizing the HLS utility library, such as the arbitrary precision library, has been enhanced. In SmartHLS 2024.2 or earlier version, the report would attribute resource consumption to the HLS utility code, which could obscure the actual source of resource usage within the user's design. For example, the table below reports resource constraint of a design that uses the arbitrary precision data types in SmartHLS 2024.2. The locations of the load operations are pointing to the library code that implements the arbitrary precision data type functionality; however, it does not help locating the source in the user code.
    +-------------------------------------+------------------------------------------------------------------------------------------------------+---------------------+
    | Operation                           | Location                                                                                             | Competing Use Count |
    +-------------------------------------+------------------------------------------------------------------------------------------------------+---------------------+
    | 'load' (5b) operation for array 'A' | line 348 of C:/Microchip/Libero_SoC_v2024.2/SmartHLS-2024.2/SmartHLS/smarthls-library/hls/ap_int.hpp | 1                   |
    | 'load' (5b) operation for array 'A' | line 348 of C:/Microchip/Libero_SoC_v2024.2/SmartHLS-2024.2/SmartHLS/smarthls-library/hls/ap_int.hpp | 2                   |
    | 'load' (5b) operation for array 'A' | line 348 of C:/Microchip/Libero_SoC_v2024.2/SmartHLS-2024.2/SmartHLS/smarthls-library/hls/ap_int.hpp | 3                   |
    +-------------------------------------+------------------------------------------------------------------------------------------------------+---------------------+
    |                                     | Total # of Competing Uses                                                                            | 3                   |
    +-------------------------------------+------------------------------------------------------------------------------------------------------+---------------------+
    
    With the report improvement in this release, the same table now looks like the following.
    +-------------------------------------+---------------------------+---------------------+
    | Operation                           | Location                  | Competing Use Count |
    +-------------------------------------+---------------------------+---------------------+
    | 'load' (5b) operation for array 'A' | line 12 of loop.cpp       | 1                   |
    | 'load' (5b) operation for array 'A' | line 12 of loop.cpp       | 2                   |
    | 'load' (5b) operation for array 'A' | line 12 of loop.cpp       | 3                   |
    +-------------------------------------+---------------------------+---------------------+
    |                                     | Total # of Competing Uses | 3                   |
    +-------------------------------------+---------------------------+---------------------+
    
  • HLS pipeline reports are enhanced to handle non-constant but bounded trip count and latency. Here is an example of the report.
    +-------------------------------------------------------------------------------------------+
    | Function: top takes 0 - 22 cycles                                                         |
    +----------+--------------------------+------------+-------------------+----+---------------+
    | Loop     | Location In Source       | Trip Count | Iteration Latency | II | Total Latency |
    +----------+--------------------------+------------+-------------------+----+---------------+
    | for_loop | line 16 of loop_test.cpp | 0 - 16     | 1                 | 1  | 0 - 16        |
    +----------+--------------------------+------------+-------------------+----+---------------+
    
Enhanced Board Support
Soft-MiV RV32 can now run on-board using SoC Flow. For more information, see Automated SOC Flow (Beta Version).

Resolved Issues

The following issues have been resolved in the 2025.1 version:
  • Fixed the invalid command name "work.configure" error message generated from co-simulation with waveform.
  • Fixed incorrect design output caused by typecasting of local array pointers.
  • Fixed co-simulation crash caused by non-flushed output stream buffers during software simulation. The problem appeared on Windows platforms only.
  • Fixed crash caused by LLVM linker merging user struct types that are isomorphic to SmartHLS's arbitrary data types together.
  • Errored out input designs that contain variable-sized storage allocation.
  • Generated warning when memory I/O operation with access size wider than target data bus is found in the design.
  • Allowed conversion between primitive array data type pointers and the size-equivalent ap_int/ap_uint array pointers through simple pointer casting in both hardware synthesis and software simulation.
  • Fixed bugs in latency estimation of pipelined loops and enhanced the accuracy and comprehensiveness of the reports.
  • Fixed crash caused by pass-by-reference argument in HLS threaded function.
  • Fixed crash that happened when a float-typed variable is used as an induction variable in a loop.
  • Fixed co-simulation bug caused by same-name functions existing at different scopes of the input design.
  • Fixed a bug in calling a stack of dataflow functions multiple times.
  • Errored out input designs that contain array of pointers as top-level function argument.
  • Enhanced '[HLS pragma] ignored ' warning messages with source code location.
  • Fixed various IDE problems.
  • Ceased the generation of unnecessary Verilog memory initialization files.