17.1.4 Synthesizing Your Design

One of the primary features of the Custom Flow is to allow you to use a third-party synthesis tool outside Libero. The custom flow supports the use of Synopsys SynplifyPro. To synthesize your project, use the following procedure:

  1. Create a new project in your Synthesis tool, targeting the same device family, die, and package as the Libero project you created.
    1. Import your own RTL files as you normally do.
    2. Set the Synthesis output to be Structural Verilog (.vm).
    Tip: Structural Verilog (.vm) is the only supported synthesis output format in PolarFire.
  2. Import Component HDL files into your Synthesis project:
    1. For each Component Manifests Report: For each file under HDL source files for all Synthesis and Simulation tools, import the file into your Synthesis Project.
  3. Import the file polarfire_syn_comps.v (if using Synopsys Synplify) from <Libero Installation location>/data/aPA5M to your Synthesis project.
  4. Import the previously generated SDC file through the Derived Constraint tool (see Appendix A—Sample SDC Constraints) into the Synthesis tool. This constraint file constrains the synthesis tool to achieve timing closure with less effort and fewer design iterations.
Important:
  • If you plan to use the same *.sdc file to constrain Place-and-Route during the design implementation phase, you must import this *.sdc into the synthesis project. This is to ensure that there are no design object name mismatches in the synthesized netlist and the Place-and-Route constraints during the implementation phase of the design process. If you do not include this *.sdc file in the Synthesis step, the netlist generated from Synthesis may fail the Place and Route step because of design object name mismatches.
    1. Import Netlist Attributes *.ndc, if any, into the Synthesis tool.
    2. Run Synthesis.
  • The location of your Synthesis tool output has the *.vm netlist file generated post Synthesis. You must import the netlist into the Libero Implementation Project to continue with the design process.