1.2.3 Activity Mode and Protocol Error Bits Are Not Implemented

The Activity Mode ACTMODE bits and the Protocol Error PERR bit in the I3CxDSTAT0 register are read-only hardcoded to 0, which does not align with the MIPI I3C specification for GETSTATUS CCC.

Work around

None.

Affected Silicon Revisions


B2	C0
X

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