Introduction

The PIC18F06/16Q20 devices you have received conform functionally to the current device data sheet (DS40002387C), except for the anomalies described in this document.

The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in the table below.

The errata described in this document will be addressed in future revisions of the PIC18F06/16Q20 silicon.

Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current.

Table . Silicon Device Identification
Part Number	Device ID	Revision ID
Part Number	Device ID	B2	C0
PIC18F06Q20	0x7A60	0xA042	0xA080
PIC18F16Q20	0x7A40	0xA042	0xA080

Important: Refer to the Device/Revision ID section in the current “PIC18FXXQ20 Family Programming Specification” (DS40002327) for more detailed information on Device Identification and Revision IDs for your specific device.

Table . Silicon Issue Summary
Module	Feature	Item No.	Issue Summary	Affected Revisions
Module	Feature	Item No.	Issue Summary	B2	C0
I²C	Bus Time-Out	CSTR Bit Is Not Cleared after Bus Time-Out	CSTR Bit Is Not Cleared after Bus Time-Out	X
	Bus Time-Out	MDR Bit Is Not Cleared after Bus Time-Out	MDR Bit Is Not Cleared after Bus Time-Out	X
	Bus Time-Out	Bus Time-Out Not Detected Properly When External Host Clock Stretches	Bus Time-Out Not Detected Properly When External Host Clock Stretches	X
	Bus Time-Out	Bus Time-Out Causes False Start/Stop	Bus Time-Out Causes False Start/Stop	X
	Clock Stretch	Clock Stretch Disable Not Working Properly	Clock Stretch Disable Not Working Properly	X
	Clock Stretch	Clock Stretching Does Not Work When the I²C and I3C Modules Share the Same Pins	Clock Stretching Does Not Work When the I²C and I3C Modules Share the Same Pins	X
	Bus Collision	Bus Collision Followed by a Stop Condition during a Transaction by an External Host Device May Hang the Bus	Bus Collision Followed by a Stop Condition during a Transaction by an External Host Device May Hang the Bus	X
	Multi-Host Arbitration	I²C Module May Hang the Bus during Multi-Host Arbitration	I²C Module May Hang the Bus during Multi-Host Arbitration	X
I3C	Bus Available and Idle Timer	I3C Bus Available/Idle Timer Does Not Start Counting until IBI/HJREQ Is Set	I3C Bus Available/Idle Timer Does Not Start Counting until IBI/HJREQ Is set	X
	Static Address SDR Mode	Static Address Match Sets DADRIF Bit in Static Address SDR Mode	Static Address Match Sets DADRIF Bit in Static Address SDR Mode	X
	Device Status	Activity Mode and Protocol Error Bits Are Not Implemented	Activity Mode and Protocol Error Bits Are Not Implemented in DSTAT0	X
	Dynamic Address Assignment	Incorrect Dynamic Address Change Interrupt Operation	Incorrect Dynamic Address Change Interrupt Operation	X
	HDR Exit	Force HDR Exit Feature Is Not Functional	Force HDR Exit Feature Is Not Functional	X
	In-Band Interrupt/Hot-Join	In-Band Interrupt/Hot-Join NACK Causes the IBI/HJ Request to Be Canceled When a Bus Time-Out Occurs	In-Band Interrupt/Hot-Join NACK Causes the IBI/HJ Request to Be Canceled When a Bus Time-Out Occurs	X
	In-Band Interrupt/Hot-Join	Passive Hot-Join/In-Band Interrupt May Cause Race Condition to Happen	Passive Hot-Join/In-Band Interrupt may cause race condition to happen	X
	Hot-Join	Hot-Join Does Not Work Properly When RETRY = `1`	Hot-Join Does Not Work Properly When RETRY = `1`	X
	Hot-Join	Incorrect Hot-Join Operation after Controller ACKs and Sends Stop	Incorrect Hot-Join Operation after Controller ACKs and Sends Stop	X
	Private Transaction One-Shot	Incorrect ACKPOS Operation with Direct CCC Write Transactions	Incorrect ACKPOS Operation with Direct CCC Write Transactions	X
	Read/Write RNW Status Bits	RNW Status Bits Are Not Sticky and Are Set for Both ACK and NACK	RNW Status Bits Are Not Sticky and Are Set for Both ACK and NACK	X
	Address Match Flags	DADRIF and SADRIF Flags Are Incorrectly Set for Direct CCCs and Private/I²C NACKs	DADRIF and SADRIF Flags Are Incorrectly Set for Direct CCCs and Private/I²C NACKs	X
	Private/I²C Transaction Acknowledge	ACKP and ACKPOS Bits Are Not Functional for Private Read and I²C Read/Write Transactions	ACKP and ACKPOS Bits Are Not Functional for Private Read and I²C Read/Write Transactions	X
	Target Reset	Target Reset Pattern Is Not Detected without a Preceding Start Condition	Target Reset Pattern Is Not Detected without a Preceding Start Condition	X
	Target Reset	Unexpected RSTACT CCC Behavior with Certain Defining Bytes	Unexpected RSTACT CCC Behavior with Certain Defining Bytes	X
	Target Reset	Target Reset Pattern May Be Detected Before a Stop Condition Occurs	Target Reset Pattern May Be Detected before a Stop Condition Occurs	X
	Target Reset	BFREE Bit Not Set after Target Reset Pattern	BFREE Bit Not Set after Target Reset Pattern	X
	CCC	Direct CCCs Read/Write from FIFO in I²C Mode	Direct CCCs Read/Write from FIFO in I²C Mode	X
	Transmit/Receive FIFO	TXFIFO and RXFIFO Are Not Cleared When the Module Is Enabled	TXFIFO and RXFIFO Are Not Cleared When the Module Is Enabled	X
	Error Detection and Recovery	TE4 Error Not Detected When Module Operates in I3C Mode	TE4 error not detected when module operates in I3C mode	X
	Error Detection and Recovery	TE0/TE1 Error Detection Cannot be Turned Off in I²C Mode	TE0/TE1 Error Detection cannot be turned off in I²C mode	X
	Error Detection and Recovery	TE0 Error Detection Does Not Take R/W Bit Into Consideration	TE0 Error Detection does not take R/W bit into consideration	X
ICSP™	Low-Voltage Programming	Low-Voltage Programming Not Possible	Low-Voltage Programming Not Possible	X
UART	UART	UART TXDE Signal May Go Low before the STOP Bit Has Been Entirely Transmitted	UART TXDE Signal May Go Low before the STOP Bit Has Been Entirely Transmitted	X
UTMR	Level-Triggered ERS Start/Reset Condition	Dead Zone Exists in Level-Triggered Start/Reset Condition When an ERS Signal Is Generated Due to an SFR Access	Dead Zone Exists in Level-Triggered Start/Reset Condition When an ERS Signal Is Generated Due to an SFR Access	X	X
UTMR	Interrupts	Interrupts Do Not Work When Leaving Debug Mode	Interrupts Do Not Work When Leaving Debug Mode	X	X
Electrical Specifications	Multi-Voltage I/O	Maximum MVIO Supply Voltage Is 3.63V	Maximum MVIO Supply Voltage Is 3.63V	X
Note: Only those issues indicated in the last column apply to the current silicon revision.