Introduction
The PIC18F06/16Q20 devices you have received conform functionally to the current device data sheet (DS40002387C), except for the anomalies described in this document.
The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in the table below.
The errata described in this document will be addressed in future revisions of the PIC18F06/16Q20 silicon.
Note: This document summarizes all silicon errata issues from
all revisions of silicon, previous as well as current.
| Part Number | Device ID | Revision ID | |
|---|---|---|---|
| B2 | C0 | ||
| PIC18F06Q20 | 0x7A60 | 0xA042 | 0xA080 |
| PIC18F16Q20 | 0x7A40 | 0xA042 | 0xA080 |
Important: Refer to the Device/Revision ID section in
the current “PIC18FXXQ20 Family Programming Specification” (DS40002327) for more detailed
information on Device Identification and Revision IDs for your specific device.
| Module | Feature | Item No. | Issue Summary | Affected Revisions | |
|---|---|---|---|---|---|
| B2 | C0 | ||||
| I2C | Bus Time-Out | 1.1.1 | CSTR Bit Is Not Cleared after Bus Time-Out | X | |
| Bus Time-Out | 1.1.2 | MDR Bit Is Not Cleared after Bus Time-Out | X | ||
| Bus Time-Out | 1.1.3 | Bus Time-Out Not Detected Properly When External Host Clock Stretches | X | ||
| Bus Time-Out | 1.1.4 | Bus Time-Out Causes False Start/Stop | X | ||
| Clock Stretch | 1.1.5 | Clock Stretch Disable Not Working Properly | X | ||
| Clock Stretch | 1.1.6 | Clock Stretching Does Not Work When the I2C and I3C Modules Share the Same Pins | X | ||
| Bus Collision | 1.1.7 | Bus Collision Followed by a Stop Condition during a Transaction by an External Host Device May Hang the Bus | X | ||
| Multi-Host Arbitration | 1.1.8 | I2C Module May Hang the Bus during Multi-Host Arbitration | X | ||
| I3C | Bus Available and Idle Timer | 1.2.1 | I3C Bus Available/Idle Timer Does Not Start Counting until IBI/HJREQ Is set | X | |
| Static Address SDR Mode | 1.2.2 | Static Address Match Sets DADRIF Bit in Static Address SDR Mode | X | ||
| Device Status | 1.2.3 | Activity Mode and Protocol Error Bits Are Not Implemented in DSTAT0 | X | ||
| Dynamic Address Assignment | 1.2.4 | Incorrect Dynamic Address Change Interrupt Operation | X | ||
| HDR Exit | 1.2.5 | Force HDR Exit Feature Is Not Functional | X | ||
| In-Band Interrupt/Hot-Join | 1.2.6 | In-Band Interrupt/Hot-Join NACK Causes the IBI/HJ Request to Be Canceled When a Bus Time-Out Occurs | X | ||
| In-Band Interrupt/Hot-Join | 1.2.7 | Passive Hot-Join/In-Band Interrupt may cause race condition to happen | X | ||
| Hot-Join | 1.2.8 | Hot-Join Does Not Work Properly When RETRY =
1 |
X | ||
| Hot-Join | 1.2.9 | Incorrect Hot-Join Operation after Controller ACKs and Sends Stop | X | ||
| Private Transaction One-Shot | 1.2.10 | Incorrect ACKPOS Operation with Direct CCC Write Transactions | X | ||
| Read/Write RNW Status Bits | 1.2.11 | RNW Status Bits Are Not Sticky and Are Set for Both ACK and NACK | X | ||
| Address Match Flags | 1.2.12 | DADRIF and SADRIF Flags Are Incorrectly Set for Direct CCCs and Private/I2C NACKs | X | ||
| Private/I2C Transaction Acknowledge | 1.2.13 | ACKP and ACKPOS Bits Are Not Functional for Private Read and I2C Read/Write Transactions | X | ||
| Target Reset | 1.2.14 | Target Reset Pattern Is Not Detected without a Preceding Start Condition | X | ||
| Target Reset | 1.2.15 | Unexpected RSTACT CCC Behavior with Certain Defining Bytes | X | ||
| Target Reset | 1.2.16 | Target Reset Pattern May Be Detected before a Stop Condition Occurs | X | ||
| Target Reset | 1.2.17 | BFREE Bit Not Set after Target Reset Pattern | X | ||
| CCC | 1.2.18 | Direct CCCs Read/Write from FIFO in I2C Mode | X | ||
| Transmit/Receive FIFO | 1.2.19 | TXFIFO and RXFIFO Are Not Cleared When the Module Is Enabled | X | ||
| Error Detection and Recovery | 1.2.20 | TE4 error not detected when module operates in I3C mode | X | ||
| Error Detection and Recovery | 1.2.21 | TE0/TE1 Error Detection cannot be turned off in I2C mode | X | ||
| Error Detection and Recovery | 1.2.22 | TE0 Error Detection does not take R/W bit into consideration | X | ||
| ICSP™ | Low-Voltage Programming | 1.3.1 | Low-Voltage Programming Not Possible | X | |
| UART | UART | 1.4.1 | UART TXDE Signal May Go Low before the STOP Bit Has Been Entirely Transmitted | X | |
| UTMR | Level-Triggered ERS Start/Reset Condition | 1.5.1 | Dead Zone Exists in Level-Triggered Start/Reset Condition When an ERS Signal Is Generated Due to an SFR Access | X | X |
| Interrupts | 1.5.2 | Interrupts Do Not Work When Leaving Debug Mode | X | X | |
| Electrical Specifications | Multi-Voltage I/O | 1.6.1 | Maximum MVIO Supply Voltage Is 3.63V | X | |
|
Note: Only those issues
indicated in the last column apply to the current silicon
revision.
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