1.2.19 TXFIFO and RXFIFO Are Not Cleared When the Module Is Enabled
The TXFIFO and RXFIFO are not reset when the module is enabled. If there is any rogue data present in the FIFO, it will continue to be there even after the user disables/enables the module.
Work around
The user can explicitly clear the TXFIFO/RXFIFO using the CLRTXB and CLRRXB bits before enabling the module.
Affected Silicon Revisions
| B2 | C0 |
| X |