7.3 Timing Sequence of UART Application

The following figures illustrate the various UART control signal timing sequences.

Figure 7-3. Power-On/Off Sequence
Figure 7-4. Timing Sequence of RX Indication after Power-On
Figure 7-5. Timing Sequence of Power-Off
Note:
  1. EEPROM clock = 100 kHz.
  2. For a byte wire, 0.01 ms x 32 clock x 2 = 640 μs.
  3. It is recommended that ramp-down time be more than 640 μs during the power-off sequence to ensure safe operation of the device.
Figure 7-6. Timing Sequence of Power-On (NACK)
Figure 7-7. Reset Timing Sequence in Case of No Response from SoC to Host MCU
Note: The MCU sends the UART command again, when the SoC is not responding to its first UART command. If the SoC is not responding to the second UART command within X ms, the MCU forces the system to reset.
Figure 7-8. Timing Sequence of Power Drop Protection
  1. It is recommended that the battery be connected on a BAT_IN pin of the SoC for the power supply.
  2. If an external power source or a power adapter is used to provide the power to the SoC (ADAP_IN), use a voltage supervisor IC.
  3. The RESET IC output pin must be open drain with delay time of ≤ 10 ms, and the recommended part is TCM809SVNB713.