18.5 Register Summary - Analog Peripheral Manager


Address	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00 ... 0x01BF	Reserved
0x01C0	APMCON	7:0	EN
0x01C1	APMPRE	7:0	PRE[7:0]
0x01C1	APMPRE	15:8	PRE[15:8]
0x01C3	APMPER	7:0	PER[7:0]
0x01C3	APMPER	15:8	PER[15:8]
0x01C5	APMSTART1	7:0	START1[7:0]
0x01C5	APMSTART1	15:8	START1[15:8]
0x01C7	APMPERS1	7:0	TEMP	ADCA	ADCD	FVR2	FVR1	BG
0x01C7	APMPERS1	15:8	ZCD	CMP2	CMP1	DAC3	DAC2	DAC1	OPA2	OPA1
0x01C9	APMSTART2	7:0	START2[7:0]
		15:8	START2[15:8]
		23:16	START2[23:16]
0x01CC	APMPERS2	7:0	TEMP	ADCA	ADCD	FVR2	FVR1	BG
0x01CC	APMPERS2	15:8	ZCD	CMP2	CMP1	DAC3	DAC2	DAC1	OPA2	OPA1
0x01CE	APMEND1	7:0	END1[7:0]
		15:8	END1[15:8]
		23:16	END1[23:16]
0x01D1	APMPERE1	7:0	TEMP	ADCA	ADCD	FVR2	FVR1	BG
0x01D1	APMPERE1	15:8	ZCD	CMP2	CMP1	DAC3	DAC2	DAC1	OPA2	OPA1
0x01D3	APMEND2	7:0	END2[7:0]
		15:8	END2[15:8]
		23:16	END2[23:16]
0x01D6	APMPERE2	7:0	TEMP	ADCA	ADCD	FVR2	FVR1	BG
0x01D6	APMPERE2	15:8	ZCD	CMP2	CMP1	DAC3	DAC2	DAC1	OPA2	OPA1
0x01D8	APMCLK	7:0							CLK[1:0]
0x01D9	APMSTATUS	7:0	TEMP	ADCA	ADCD	FVR2	FVR1	BG
0x01D9	APMSTATUS	15:8	ZCD	CMP2	CMP1	DAC3	DAC2	DAC1	OPA2	OPA1