3.6.31 MPDDRC Write Protection Status Register

A write-only register has been read (warning).

MPDDRC is enabled and a write access has been performed on a read-only register (warning).

Access to an undefined address (warning).

Abnormal use of MPDDRC user interface when memory device is already configured and initialized, i.e., if MPDDRC_RTR.COUNT > 0 (error).

No software error has occurred since the last read of MPDDRC_WPSR.

A software error has occurred since the last read of MPDDRC_WPSR. The field SWE details the type of software error. The associated incorrect software access is reported in the field WPVSRC (if WPVS=0).

In the registers listed below, no peripheral internal sequencer error has occurred or no single error has occurred since the last read of MPDDRC_WPSR:

• Mode register (MPDDRC_MR)

• Memory Device register (MPDDRC_MD

• Refresh Timer register (MPDDRC_RTR)

• Timing Parameter 0/1/2 registers (MPDDRC_TPR0/1/2)

• Low-Power register (MPDDRC_LPR)

• Configuration register (MPDDRC_CR)

• OCMS KEY1 register (MPDDRC_OCMS_KEY1)

• OCMS KEY2 register (MPDDRC_OCMS_KEY2)

The clock monitoring circuitry has not been corrupted since the last read of MPDDRC_WPSR. Under normal operating conditions, this bit is always cleared.

The clock monitoring circuitry has been corrupted since the last read of MPDDRC_WPSR. This flag can only be set in case of an abnormal clock signal waveform (glitch).

No write protection violation occurred since the last read of this register (MPDDRC_WPSR).

A write protection violation occurred since the last read of this register (MPDDRC_WPSR). If this violation is an unauthorized attempt to write a control register, the associated violation is reported into the WPVSRC field.