25.3.3.1 Register Synchronization Categories
The TCF core is operating asynchronous with the peripheral clock. Any access to the control and data register therefore needs to be synchronized to the core domain. This is done differently for different register categories.
Some control registers are not allowed to be changed while the timer/counter is running (enable-protected).
| Double-Buffered Registers | Enable-Protected Registers | Normal I/O Registers |
|---|---|---|
| CTRLA | CTRLB | INTCTRL |
| CTRLC | EVCTRL | INTFLAGS |
| CTRLD | STATUS | |
| CNT (CNT/PER) | DBGCTRL | |
| CMP (CMP0/CMP1) |
Double-Buffered Registers
The double-buffered registers have their separate busy flag in the STATUS register. When the register is written this triggers a synchronization to the core domain and will set the corresponding busy flag. The busy bits are cleared when completing the synchronization. Registers are write-protected while the synchronization is ongoing.
For the CNT and CMP registers larger than 8-bit, the synchronization starts when writing the MSB. When the TCF operates in 8-bit PWM mode, the individual bytes in CNT and CMP registers are synchronized separately.
The control and CNT register synchronization are done as soon as the registers are written. Compare registers are updated at overflow (UPDATE). The busy flag is set until the UPDATE condition occurs. See the figure below. If immediate synchronization is wanted, this can be forced by issuing an UPDATE through the COMMAND bit field in the TCFn.CTRLD register.
As long as the CNT register is not written, the register is continuously updated from the core domain. After wake-up from sleep, the CNTBUSY bit remains set until the CNT value is updated with the latest value in the core domain.
Enable Protected Registers
The enable-protected registers can only be written when the ENABLE bit in the TCFn.CTRLA
register is written to '0'.