12.5.10 PLL Control B
| Name: | PLLCTRLB |
| Offset: | 0x11 |
| Reset: | 0x00 |
| Property: | Configuration Change Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKDIV | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – CLKDIV PLL Output Clock Divider
This bit field controls the PLL Output Clock division for clock used by asynchronous peripherals.
Note: Using DIV2 will
also remove any duty cycle error from the PLL. This bit can be changed while PLL is
running.
| Value | Name | Description |
|---|---|---|
| 0 | NONE | Use undivided PLL clock. |
| 1 | DIV2 | Divide PLL clock by two. |