12.5.1 Main Clock Control A
| Name: | MCLKCTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | Configuration Change Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLKOUT | CLKSEL[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 7 – CLKOUT Main Clock Out
This bit controls whether the main clock is available on the Main Clock Out (CLKOUT) pin when the main clock is running.
| Value | Description |
|---|---|
| 0 | The main clock is not available on the CLKOUT pin |
| 1 | The main clock is available on the CLKOUT pin |
Bits 3:0 – CLKSEL[3:0] Clock Select
This bit field controls the source for the Main Clock (CLK_MAIN).
| Value | Name | Description |
|---|---|---|
| 0x0 | OSCHF | Internal high-frequency oscillator |
| 0x1 | OSC32K | 32.768 kHz internal oscillator |
| 0x2 | XOSC32K | 32.768 kHz external clock or 32.768 kHz external crystal oscillator, depending on the SEL bit in XOSC32KCTRLA |
| 0x3 | EXTCLK | External clock |
| 0x4 | PLL | PLL Oscillator |
| Other | Reserved | Reserved |