23.5.7 Control Register F Clear
| Name: | CTRLFCLR |
| Offset: | 0x06 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMP3BV | CMP2BV | CMP1BV | CMP0BV | PERBV | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bits 1, 2, 3, 4 – CMPnBV Compare n Buffer Valid
The CMPnBV bits are set when a new value is written to the corresponding
TCEn.CMPnBUF register. These bits automatically clear on an
UPDATE condition.
Bit 0 – PERBV Period Buffer Valid
This bit is set when a new value is written to the TCEn.PERBUF register. This bit
automatically clears on an UPDATE condition.