23.5.6 Control Register E Set


Bit	7	6	5	4	3	2	1	0
					CMD[1:0]		LUPD	DIR
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 3:2 – CMD[1:0] Command

This bit field is used to send software commands to the TCEn. The command bit field clears automatically by hardware after command execution and always reads as ‘0’.

Value	Name	Description
0x0	NONE	No command
0x1	UPDATE	Force update
0x2	RESTART	Force restart
0x3	RESET	Force hard Reset (ignored if the timer/counter is enabled)

Bit 1 – LUPD Lock Update

Locking the update ensures that all buffers are valid before performing an update. Writing a ‘1’ to this bit will cause the LUPD to be set, and the Update is locked.

Value	Description
0	The buffered registers are updated as soon as an `UPDATE` condition has occurred
1	No update of the buffered registers is performed, even though an `UPDATE` condition has occurred. This setting will not prevent an update issued by the Command bit field.

Bit 0 – DIR Counter Direction

Usually, this bit is controlled in hardware by the Waveform Generation mode or by event actions, but can also be changed from the software. Writing a ‘1’ to this bit will set the DIR bit, and the counter will count down.

Value	Description
0	The counter is counting up (incrementing)
1	The counter is counting down (decrementing)

Name:	CTRLESET
Offset:	0x05
Reset:	0x00
Property:	-