4.1.4 LPDDR2-SDRAM/LPDDR3-SDRAM Initialization

The initialization sequence is generated by software. The low-power DDR2-SDRAM and low-power DDR3-SDRAM devices are initialized by the following sequence:

Table 4-4. LPDDR2-SDRAM/LPDDR3-SDRAM Initialization
Step	Action	Register	Setting
1	Program the memory device type	MPDDRC_MD	MD = 7 (for LPDDR2), MD = 5 (for LPDDR3), DBW = 0 (32 bits)
2	Program the shift sampling value	MPDDRC_RD_DATA_PATH	Section SDRAM Controller Configuration provides values for these fields. These values depend on the DDR clock.
3	Program LPDDR2-SDRAM features	MPDDRC_CR MPDDRC_TPR0 MPDDRC_TPR 1
4	Program DS, SEG_MASK and BK_MASK_PASR	MPDDRC_LPDDR23_LPR	–
5	Issue a NOP command⁽²⁾	MPDDRC_MR	MODE = 1
6	1 μs delay⁽¹⁾	–	–
7	Issue a NOP command⁽²⁾	MPDDRC_MR	MODE = 1
8	200 μs delay⁽¹⁾	–	–
9	Issue a Reset command⁽²⁾	MPDDRC_MR	MODE = 7, MRS = 63
10	500 μs delay⁽¹⁾	–	-–
11	Issue a Calibration command⁽²⁾	MPDDRC_CR MPDDRC_MR	ZQ = 3, after command ack ZQ = 2 MODE = 7, MRS = 10
12	Issue a Mode register Write command⁽²⁾	MPDDRC_MR	MODE = 7, MRS = 1
13	Issue a Mode register Write command⁽²⁾	MPDDRC_MR	MODE = 7, MRS = 2
14	Issue a Mode register Write command⁽²⁾	MPDDRC_MR	MODE = 7, MRS = 3
15	Issue a Mode register Write command⁽²⁾	MPDDRC_MR	MODE = 7, MRS = 16
16	Write ‘1’ to bits 17 and 16 in SFR_DDRCFG	SFR_DDRCFG	Bit 17 = 1, Bit 16 = 1
17	Issue a NOP command⁽²⁾	MPDDRC_MR	MODE = 1
18	Issue a Mode register Read command⁽²⁾	MPDDRC_MR	MODE = 7, MRS = 5
19	Issue a Mode register Read command⁽²⁾	MPDDRC_MR	MODE = 7, MRS = 6
20	Issue a Mode register Read command⁽²⁾	MPDDRC_MR	MODE = 7, MRS = 8
21	Issue a Mode register Read command⁽²⁾	MPDDRC_MR	MODE = 7, MRS = 0
22	Provide a Normal Mode command⁽²⁾	MPDDRC_MR	MODE = 0
23	Write ‘0’ to bits 17 and 16 in SFR_DDRCFG	SFR_DDRCFG	Bit 17 = 0, Bit 16 = 0
24	Write the refresh rate in COUNT field	MPDDRC_RTR	COUNT = Trefi/Tck

Note:

To issue a delay: 
- disable interrupts; 
- compute a deadline = ROUND_INT_DIV((timer_channel_freq/1000)*count, 1000), where count is the delay in µs;
- start a timer and wait for the timer to reach the deadline; 
- enable interrupts.
After setting the MODE and MRS fields, read MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access at any address to acknowledge the command.

Refer to chapter ”Multiport DDR-SDRAM Controller (MPDDRC)” of the SAMA5D2 Series data sheet for more information.

AN2717

4.1.4 LPDDR2-SDRAM/LPDDR3-SDRAM Initialization