4.1.2 DDR2-SDRAM Initialization

The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized by the following sequence:

Table 4-2. DDR2-SDRAM Initialization
Step	Action	Register	Setting
1	Program the memory device type	MPDDRC_MD	MD = 6 (for DDR2), DBW = 0 (32 bits)
2	Program the shift sampling value	MPDDRC_RD_DATA_PATH	Section SDRAM Controller Configuration provides values for these fields. These values depend on the DDR clock.
3	Program DDR2-SDRAM features	MPDDRC_CR MPDDRC_TPR0 MPDDRC_TPR1 MPDDRC_TPR2
4	Issue a NOP command⁽⁴⁾	MPDDRC_MR	MODE = 1
5	200 μs delay⁽¹⁾	–	–
6	Issue a NOP command⁽⁴⁾	MPDDRC_MR	MODE = 1
7	Issue an All Banks Precharge command⁽⁴⁾	MPDDRC_MR	MODE = 2
8	Issue an EMRS2 cycle⁽²⁾	MPDDRC_MR	MODE = 5
9	Issue an EMRS3 cycle⁽²⁾	MPDDRC_MR	MODE = 5
10	Issue an EMRS1 cycle⁽²⁾	MPDDRC_MR	MODE = 5
11	2 μs delay⁽¹⁾	–	–
12	Write a ‘1’ to the DLL bit	MPDDRC_CR	DLL = 1
13	Issue a Mode Register Set (MRS) cycle⁽³⁾	MPDDRC_MR	MODE = 3
14	Issue an All Banks Precharge command⁽⁴⁾	MPDDRC_MR	MODE = 2
15	Provide two autorefresh (CBR) cycles⁽⁴⁾	MPDDRC_MR	MODE = 4
16	Write a ‘0’ to the DLL bit	MPDDRC_CR	DLL = 0
17	Issue a Mode Register Set (MRS) cycle⁽³⁾	MPDDRC_MR	MODE = 3
18	Configure the OCD field to 7	MPDDRC_CR	OCD = 7
19	Issue an EMRS1 cycle⁽²⁾	MPDDRC_MR	MODE = 5
20	Configure the OCD field to 0	MPDDRC_CR	OCD = 0
21	Issue an EMRS1 cycle⁽²⁾	MPDDRC_MR	MODE = 5
22	Provide a Normal Mode command⁽⁴⁾	MPDDRC_MR	MODE = 0
23	Write the refresh rate in COUNT field	MPDDRC_RTR	COUNT = Trefi/Tck

Note:

To issue a delay: 
- disable interrupts; 
- compute a deadline = ROUND_INT_DIV((timer_channel_freq/1000)*count, 1000), where count is the delay in µs;
- start a timer and wait for the timer to reach the deadline;
- enable interrupts.
To issue an Extended Mode Register Set (EMRS) cycle, after setting the MODE field to 5, read MPDDRC_MR and add a memory barrier assembler instruction just after the read. Then perform a write access to the DDR2-SDRAM device so that the BA[1:0] signals are as follows: 
- BA[1] is set to 0, BA[0] is set to 1 for EMRS1;
- BA[1] is set to 1, BA[0] is set to 0 for EMRS2;
- BA[1] is set to 1, BA[0] is set to 1 for EMRS3.
  The address at which the write access is issued in order to acknowledge the command needs to be calculated so that the BA[1:0] signals are in the right state for an EMRS cycle.
After setting the MODE field, read MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access to acknowledge the command so that BA[2:0] signals are set to 0 (write at BASE_ADDRESS_DDR).
After setting the MODE field, read MPDDRC_MR and add a memory barrier assembler instruction just after the read. Perform a write access at any address to acknowledge the command.

Refer to chapter ”Multiport DDR-SDRAM Controller (MPDDRC)” of the SAMA5D2 Series data sheet for more information.

AN2717