33.9.1 Control A

0: No effect.

1: The chip select will be de-asserted after the character written in TD has been transferred.

Writing a '0' to this bit disables the QSPI.

Writing a '1' to this bit enables the QSPI to transfer and receive data.

As soon as ENABLE is reset, QSPI finishes its transfer.

All pins are set in input mode and no data is received or transmitted.

If a transfer is in progress, the transfer is finished before the QSPI is disable.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit resets the QSPI. A software-triggered hardware reset of the QSPI interface is performed.

DMAC channels are not affected by software reset.