33.9.8 Interrupt Flag Status and Clear

This bit is set when an Instruction End has been detected.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the flag.

The bit is set when a Chip Select Rise has been detected.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the flag.

This bit is set when an ERROR has occurred.

An ERROR occurs when RXDATA is loaded at least twice from the serializer.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the flag.

0: As soon as data is written in TXDATA.

1: TXDATA and internal shifter are empty. If a transfer delay has been defined, TXC is set after the completion of such delay.

0: Data has been written to TXDATA and not yet transferred to the serializer.

1: The last data written in the TXDATA has been transferred to the serializer.

This bit is '0' when the QSPI is disabled or at reset.

The bit is set as soon as ENABLE bit is set.

0: No data has been received since the last read of RXDATA.

1: Data has been received and the received data has been transferred from the serializer to RXDATA since the last read of RXDATA.