18.4.6 Peripheral Clock Generator 1
The CFGPCLKGEN1 dictates the peripheral clock selection described in the Clock System chapter.
There is no Flash location for this register because the purpose of this register is to provide an application-based peripheral clocking selection. This is best handled in the application software drivers.
| Name: | CFGPCLKGEN1 |
| Offset: | 0x60 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CM4TD | CM4TCSEL[2:0] | TC23CD | TC23CSEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TCC12CD | TCC12CSEL[2:0] | S23D | SERCOM23CSEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| S01CD | SERCOM01CSEL[2:0] | MCD | FREQMMCSEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RCD | FREQMRCSEL[2:0] | EICCD | EICCSEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – CM4TD CM4 Trace Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] = ‘
00’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 30:28 – CM4TCSEL[2:0] CM4 Trace Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] = ‘
00’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 27 – TC23CD TC2 and TC3 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] = ‘
00’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 26:24 – TC23CSEL[2:0] TC2 and TC3 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] = ‘
00’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 23 – TCC12CD TCC1 and TCC2 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] = ‘
00’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 22:20 – TCC12CSEL[2:0] TCC1 and TCC2 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] = ‘
00’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 19 – S23D SERCOM2 and SERCOM3 Peripheral Clock Disable
Note:
- This field is only writable when CFGLOCK[1:0] =
‘
00’. - This bit is only applicable in 48-pin variants.
| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 18:16 – SERCOM23CSEL[2:0] SERCOM2 and SERCOM3 Peripheral Clock Selection
Note:
- This field is only writable when CFGLOCK[1:0] =
‘
00’. - This bit is only applicable in 48-pin variants.
| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 15 – S01CD SERCOM0 and SERCOM1 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 14:12 – SERCOM01CSEL[2:0] SERCOM0 and SERCOM1 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 11 – MCD FREQM Measurement Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 10:8 – FREQMMCSEL[2:0] FREQM Measurement Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 7 – RCD FREQM Reference Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 6:4 – FREQMRCSEL[2:0] FREQM Reference Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 3 – EICCD EIC Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 2:0 – EICCSEL[2:0] EIC Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |