18.4.8 Peripheral Clock Generator 3
The CFGPCLKGEN3 dictates the peripheral clock selection described in the Clock System chapter.
Note that the following bits EVSYSCX range from 9-12 which corresponds to channel 8 to 11. There is no Flash location for this register because the purpose of this register is to provide an application-based peripheral clocking selection. This is best handled in the application software drivers.
| Name: | CFGPCLKGEN3 |
| Offset: | 0x80 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TC1CD | TC1CSEL[2:0] | TC0CD | TC0CSEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TCC0CD | TCC0CSEL[2:0] | ACCD | ACCLKSEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| C12D | EVSYSC12SEL[2:0] | C11D | EVSYSC11SEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| C10D | EVSYSC10SEL[2:0] | C9D | EVSYSC9SEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – TC1CD TC1 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 30:28 – TC1CSEL[2:0] TC1 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 27 – TC0CD TC0 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 26:24 – TC0CSEL[2:0] TC0 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 23 – TCC0CD TCC0 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 22:20 – TCC0CSEL[2:0] TCC0 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 19 – ACCD AC Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 18:16 – ACCLKSEL[2:0] AC Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 15 – C12D EVSYSC12 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 14:12 – EVSYSC12SEL[2:0] EVSYSC12 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 11 – C11D EVSYSC11 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 10:8 – EVSYSC11SEL[2:0] EVSYSC11 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 7 – C10D EVSYSC10 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 6:4 – EVSYSC10SEL[2:0] EVSYSC10 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 3 – C9D EVSYSC9 Peripheral Clock Disable
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 2:0 – EVSYSC9SEL[2:0] EVSYSC9 Peripheral Clock Selection
Note: This field is only writable
when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |