18.4.1 Configuration Control Register 0

The CFGLOCK[1:0] register bits are writable only when CFGLOCK[0] = 1’b0.

The IOLOCK, PMDLOCK and PGLOCK register bits can only be cleared on a system reset. Thereafter, it is controlled as described above.

This register is loaded with trusted data from FBCFG1 during the pre-boot period. Trusted data from Flash means when there is no BCFG* fail status and BINFOVALID = 0 during Flash configuration word reads. If accompanied by a fail status or blank/erase indication, then reset values (described in the register description below) are retained and new values from FBCFG1 are not loaded.

Under all conditions, Flash loading is omitted for the following bits in the CFGCON0 and HPLUGDIS register:

IOLOCK
CFGLOCK[1:0]
PMDLOC
PGLOCK
PMULOCK
JTAGEN

Name:	CFGCON0(L)
Offset:	0x00
Reset:	0x7100000b
Property:	-


Bit	31	30	29	28	27	26	25	24
		FRECCDIS	FECCCON/ECCCTL[1:0]		ADCFCEN	INT0P	INT0E	PCM
Access		R/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset		1	1	1	0	0	0	1


Bit	23	22	21	20	19	18	17	16
	SLRTEN2	SLRTEN1	SLRTEN0	HPLUGDIS	SMBUSEN2	SMBUSEN1	SMBUSEN0	VBCMODE
Access	R/W/L	R/W/L	R/W/L	R/W	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CFGLOCK[1:0]		IOLOCK	PMDLOCK	PGLOCK	PMULOCK	RTCOUT_ALTEN	RTCIN0_ALTEN
Access	R/W/L	R/W/L	R/S/L	R/S/L	R/S/L	R/S/L	R/W/L	R/W/L
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CPENFILT	ACCMP1_ALTEN	GPSOSCE*	ADCOPVR	JTAGEN	TROEN	SWOEN	TDOEN
Access	R/W/L	R/W/L	R/W/L	R/W	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	0	0	0	1	0	1	1

Bit 30 – FRECCDIS Flex RAM ECC Control

Note:

This bit is only writable when CFGLOCK[1:0] is ‘00’.
Only a read-only fuse bit, sets the initialization value of RAMECC Control. “True” RAMECC override is available in RAMECC module.

Value	Description
1	ECC is disabled
0	ECC is enabled

Bits 29:28 – FECCCON/ECCCTL[1:0] Flash ECC Control

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
11	ECC and dynamically ECC are disabled
10	ECC and dynamically ECC are disabled
01	Dynamically ECC is enabled
00	ECC is enabled (NVMOP = Word Programming disabled)

Bit 27 – ADCFCEN ADC FC Channel Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Exclusive ADC FC Channel Enable (Disables all second/third class channels)
0	ADC FC Channel Disable (Only second/third class channels are enabled)

Bit 26 – INT0P INT0P Polarity

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	INT0 Polarity (Positive)
0	INT0 Polarity (Negative)

Bit 25 – INT0E INT0 Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	INT0 is enabled
0	INT0 is disabled

Bit 24 – PCM PCHE I/D Cacheable Mode

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Always enabled from outside. Can be further enabled/disabled by PCHE SFR registers.
0	The cache-ability is controlled by the CPU via HPROT[3]. This feature is not available on all the ARM cores.

Bit 23 – SLRTEN2 SLRT Enable for SERCOM2

Note:

This bit is only writable when CFGLOCK[1:0] is ‘00’.
This bit is only applicable in 48-pin variants.

Value	Description
1	Slew rate is enabled
0	Slew rate is disabled

Bit 22 – SLRTEN1 SLRT Enable for SERCOM1

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Slew rate is enabled
0	Slew rate is disabled

Bit 21 – SLRTEN0 SLRT Enable for SERCOM0

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Slew rate is enabled
0	Slew rate is disabled

Bit 20 – HPLUGDIS Hot Plugging Disable (outside fuse loading)

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Hot Plugging is disabled
0	Hot Plugging is enabled

Bit 19 – SMBUSEN2 SMBus Enable for SERCOM2

Note:

This bit is only writable when CFGLOCK[1:0] is ‘00’.
This bit is only applicable in 48-pin variants.

Value	Description
1	SMBus is enabled
0	SMBus is disabled

Bit 18 – SMBUSEN1 SMBus Enable for SERCOM1

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	SMBus is enabled
0	SMBus is disabled

Bit 17 – SMBUSEN0 SMBus Enable for SERCOM0

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	SMBus is enabled
0	SMBus is disabled

Bit 16 – VBCMODE VBC Operating Mode

Note:

This bit is only writable when CFGLOCK[1:0] is ‘00’.
Do not change this field if there are pending accesses to VDDBKUPCORE memory map. Failing to do so may result in unexpected data.

Value	Description
1	Indirect addressing. The VDDBKUPCORE IO mapped using PMU Controller.
0	Direct addressing. The VDDBKUPCORE memory mapped on PB-Bridge-B.

Bits 15:14 – CFGLOCK[1:0] Configuration Register Lock

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’ or ‘10’.

Value	Description
11	All NVR memory self-writes, Boot Configuration (BCFG0) and System Configuration registers (CFG* and USER_ID) are locked and cannot be written – CFGLOCK value cannot be changed.
10	All NVR memory self-writes, Boot Configuration (BCFG0) and System Configuration registers (CFG* and USER_ID) are locked and cannot be written – CFGLOCK value can be changed.
01	Reserved for future use
00	All NVR memory self-writes, Boot Configuration (BCFG0) and System Configuration registers (CFG* and USER_ID) are not locked and can be written – CFGLOCK value can be changed.

Bit 13 – IOLOCK I/O Lock

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	I/O Remap SFR bits are locked and cannot be modified
0	I/O Remap SFR are not locked and can be modified

Bit 12 – PMDLOCK Peripheral Module Disable (PMD) Lock

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	PMDx SFR bits are locked and cannot be modified
0	PMDx SFR bits are not locked and can be modified

Bit 11 – PGLOCK Permission Group Lock

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	CFGPG SFR bits are locked and cannot be modified
0	CFGPG SFR bits are not locked and can be modified

Bit 10 – PMULOCK PMU Controller Register Lock

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	PMU* SFR bits are locked and cannot be modified
0	PMU* SFR bits are not locked and can be modified

Bit 9 – RTCOUT_ALTEN RTCOUT Alternate Enable

Note:

This bit is only writable when CFGLOCK[1:0] is ‘00’.
RTC alternate output is unavailable on PA10 in sleep modes (Deep Sleep and Extreme Deep Sleep).

Value	Description
1	RTC/OUT is available on PA10
0	RTC/OUT is available on PA4

Bit 8 – RTCIN0_ALTEN RTCIN0 Alternate Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	RTC/IN0 is available on PA9
0	RTC/IN0 is available on PA3

Bit 7 – CPENFILT ADC CP Filter Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	ADC CP filter is enabled
0	ADC CP filter is disabled

Bit 6 – ACCMP1_ALTEN AC CMP1 Alternate Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	AC/CMP1 Out is available on PA6
0	AC/CMP1 Out is available on PA1

Bit 5 – GPSOSCE* GPIO/SOSC Enable* This bit is not applicable to 48-pin variants.

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	SOSC is selected
0	GPIO is selected

Bit 4 – ADCOPVR ADC Charge Pump Override

Note:

This bit is only writable when CFGLOCK[1:0] is ‘00’.
This bit is not fuse loadable.

Value	Description
1	Overriden (software controlled)
0	Hardware controlled

Bit 3 – JTAGEN JTAG Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	JTAG port is enabled
0	JTAG port is disabled

Bit 2 – TROEN Trace Output Enable

Note:

When CFGCON1.TRCEN = 0, the value of this bit is ignored but has the effect of being ‘0’.
This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Starts Trace Clock and enables Trace Outputs (Trace probe must be present)
0	Stops Trace Clock and disables Trace Outputs

Bit 1 – SWOEN SWO enable on 2-wire debug interface

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	SWO is enabled
0	SWO is disabled

Bit 0 – TDOEN TDO enable for 2-wire JTAG

Implementing the JTAG protocol over the 2-wire interface requires four 2-wire clocks for each TCK if TDO is required. However, if the values shifted out TDO are predetermined, then TDO can be disabled, saving two 2-wire clocks.

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	2-wire JTAG protocol uses TDO (Four phase (Full Duplex) protocol)
0	2-wire JTAG protocol does not use TDO (Two phase (Half Duplex) protocol)