18.4.2 Configuration Control Register 1

This register is loaded with trusted data from FBCFG2 during the pre-boot period. Thereafter, it is controlled as described above.

Trusted data from Flash means when there is no BCFG* fail status during Flash configuration word reads. If accompanied by fail status or blank/erase indication, then reset values (described in the register description below) are retained, and new values from FBCFG2 are not loaded.

Under all conditions, Flash loading is omitted for the following bits in the CFGCON1 register:

DEBUG[1:0]

Name:	CFGCON1(L)
Offset:	0x10
Reset:	0x1f00443b
Property:	-


Bit	31	30	29	28	27	26	25	24
		CLKZBREF	QSPIDDRM	WDTPSS[4:0]
Access		R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset		0	0	1	1	1	1	1


Bit	23	22	21	20	19	18	17	16
	I2CDSEL2	I2CDSEL1	I2CDSEL0	CCL_OE	SCOM2_HSEN	SCOM1_HSEN	SCOM0_HSEN	QSPI_HSEN
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	QSCHE_EN	SMCLR	SLRCTRL2	SLRCTRL1	SLRCTRL0	CLASSBDIS	CMP1_OE	CMP0_OE
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	1	0	0	0	1	0	0


Bit	7	6	5	4	3	2	1	0
	ZBTWKSYS		TRCEN	ICESEL[1:0]			DEBUG[1:0]
Access	R/W/L		R/W/L	R/W/L	R/W/L		R/W/L	R/W/L
Reset	0		1	1	1		1	1

Bit 30 – CLKZBREF External Reference Clock Zigbee Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Enable clk_zb_to_ext on PPS.REFO1
0	No clk_zb_to_ext on PPS.REFO1, PPS.REFO1 is unchanged

Bit 29 – QSPIDDRM QSPI DDR Mode Clock Enable

Note:

When using the QSPI DDR Mode, System Clock (SYS_CLK) must be <= 48 MHz.
This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	QSPI DDR mode clock is enabled
0	Disabled

Bits 28:24 – WDTPSS[4:0] Watchdog Timer Post-scale Select Sleep bits

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
10100	1:1048576
10011	1:524288
10010	1:262144
10001	1:131072
10000	1:65536
01111	1:32768
01110	1:16384
01101	1:8192
01100	1:4096
01011	1:2048
01010	1:1024
01001	1:512
01000	1:256
00111	1:128
00110	1:64
00101	1:32
00100	1:16
00011	1:8
00010	1:4
00001	1:2
00000	1:1

Bit 23 – I2CDSEL2 I2C Delay Select for SERCOM2

Note:

This bit is only writable when CFGLOCK[1:0] is ‘00’.
This bit is only applicable in 48-pin variants.

Value	Description
1	I²C delay is enabled
0	I²C delay is disabled

Bit 22 – I2CDSEL1 I2C Delay Select for SERCOM1

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	I²C delay is enabled
0	I²C delay is disabled

Bit 21 – I2CDSEL0 I2C Delay Select for SERCOM0

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	I²C delay is enabled
0	I²C delay is disabled

Bit 20 – CCL_OE CCL Pads (via PPS) Output Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	CCL pads (via PPS) output is enabled
0	CCL pads (via PPS) output is disabled

Bit 19 – SCOM2_HSEN SERCOM2 (Direct) Enable

Note:

This bit is only writable when CFGLOCK[1:0] is ‘00’.
This bit is only applicable in 48-pin variants.

Value	Description
1	Direct mode (High-Speed) is enabled
0	Via PPS is enabled

Bit 18 – SCOM1_HSEN SERCOM1 (Direct) Enable

Note:

This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Direct mode (High-Speed) is enabled
0	Via PPS is enabled

Bit 17 – SCOM0_HSEN SERCOM0 (Direct) Enable

Note:

This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Direct mode (High-Speed) is enabled
0	Via PPS is enabled

Bit 16 – QSPI_HSEN QSPI (Direct) Enable

Note:

This bit is only writable when CFGLOCK[1:0] is ‘00’.
This bit is only applicable in 48-pin variants.

Value	Description
1	Direct Mode (High-Speed) is enabled
0	Via PPS is enabled

Bit 15 – QSCHE_EN QSPI Address Space Cache Attribute

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Cache attribute is enabled
0	Caching is disabled

Bit 14 – SMCLR Selects CRU handling of MCLR Control

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’ or ‘10’.

Value	Description
1	Legacy mode (system clear does not reset all state of device)
0	MCLR causes a faux POR

Bit 13 – SLRCTRL2 I2C Delay Select for SERCOM2

Note:

This bit is only writable when CFGLOCK[1:0] is ‘00’.
This bit is only applicable in 48-pin variants.

Value	Description
1	Slew rate control is configured via SERCOM configuration
0	Slew rate control is configured via GPIO configuration

Bit 12 – SLRCTRL1 I2C Delay Select for SERCOM1

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Slew rate control is configured via SERCOM configuration
0	Slew rate control is configured via GPIO configuration

Bit 11 – SLRCTRL0 I2C Delay Select for SERCOM0

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Slew rate control is configured via SERCOM configuration
0	Slew rate control is configured via GPIO configuration

Bit 10 – CLASSBDIS Disable CLASSB Device Functionality

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	CLASSB functions are disabled
0	CLASSB functions are enabled

Bit 9 – CMP1_OE Analog Comparator-1 Output Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	AC1 Output is enabled
0	AC1 Output is disabled

Bit 8 – CMP0_OE Analog Comparator-0 Output Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	AC0 Output is enabled
0	AC0 Output is disabled

Bit 7 – ZBTWKSYS Zigbee Bluetooth Subsystem External Wake-up source

Note:

Write-only bit, with read-as-zero; when written to ‘1’, creates one clk_lp_cycle wide pulse on Zigbee Bluetooth Subsystem.external_NMI0 pin. This enables external system wake-up to Bluetooth subsystem. This allows CPU and Bluetooth subsystem wake-up/sleep to be independent of each other.
Flash fuse loading is excluded for this bit.

Bit 5 – TRCEN Trace Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Trace features in the CPU are enabled
0	Trace features in the CPU are disabled

Bits 4:3 – ICESEL[1:0] EMUC/EMUD Communication Channel Select

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
11	ICE EMUC1/EMUD1 pins are shared with PGC1/PGD1
10	ICE EMUC2/EMUD2 pins are shared with PGC2/PGD2
01	ICE EMUC3/EMUD3 pins are shared with PGC3/PGD3 (Not used on this device)
00	ICE EMUC4/EMUD4 pins are shared with PGC4/PGD4

Bits 1:0 – DEBUG[1:0] Background Debugger Access Selection

Note:

JTAGEN = 0 prevents 4-wire JTAG Debugging but not EMUC/EMUD debugging.
If CPN = 0, then the JTAG TAP controller denies access to the EJTAG TAP Controller (i.e., the SWTAP command is ignored) and, therefore, external access to the debugging features is denied.
This bit is only writable when CFGLOCK[1:0] = ‘00’.

Value	Description
11	4-wire JTAG I/F is enabled; EMUC/EMUD is disabled; ICD module is disabled
10	4-wire JTAG I/F is enabled; EMUC/EMUD is disabled; ICD module is enabled
01	EMUC/EMUD is enabled; 4-wire JTAG I/F is disabled; ICD module is disabled
00	EMUC/EMUD is enabled; 4-wire JTAG I/F is disabled; ICD module is enabled