18.4.4 Configuration Control Register 4

This register is loaded with trusted data from FBCFG4/DEVCFG4 during the pre-boot period.

Trusted data from Flash means when there is no BCFG* fail status during Flash configuration word reads. If accompanied by fail status BCFGFAIL (RCON[26]) or blank/erase indication, then reset values (described in the following register description) are retained and new values from FBCFG4 are not loaded.

Name:	CFGCON4(L)
Offset:	0x40
Reset:	0x840e4000
Property:	-


Bit	31	30	29	28	27	26	25	24
	RTCNTM_CSEL	LPOSCEN	UVREGROVR	DSBITEN	DSWDTEN	DSWDTLPRC	DSWDTPS[4:3]
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	1	0	0	0	0	1	0	0


Bit	23	22	21	20	19	18	17	16
	DSWDTPS[2:0]			DSZPBOREN	CPEN_DLY[2:0]			RTCEVTYPE
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	0	0	0	1	1	1	0


Bit	15	14	13	12	11	10	9	8
	MLPCLK_MOD	VBKP_DIVSEL	VBKP_32KCSEL[1:0]		VBKP_1KCSEL	RTCEVENT_EN	RTCEVENTSEL[1:0]
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	1	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SOSC_CFG[7:0]
Access	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L	R/W/L
Reset	0	0	0	0	0	0	0	0

Bit 31 – RTCNTM_CSEL RTCC Counter Mode Clock Select

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Raw 32 KHz clock
0	Processed 32 KHz clock

Bit 30 – LPOSCEN Low Power (Secondary) Oscillator Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Low Power (Secondary) Oscillator, also at Reset is enabled
0	Low Power (Secondary) Oscillator is disabled

Bit 29 – UVREGROVR ULPVREG Retention Mode Override

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	ULPVREG forced in the Retention mode
0	ULPVREG controlled by XDS/DS FSM

Bit 28 – DSBITEN Deep Sleep Bit Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	DS bit in DSCON is enabled
0	DS bit in DSCON is disabled

Bit 27 – DSWDTEN Deep Sleep Watchdog Timer Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	DSWDT during deep sleep is enabled
0	DSWDT during deep sleep is disabled

Bit 26 – DSWDTLPRC Deep Sleep Watchdog Timer Reference Clock Select

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Select LPRC as DSWDT reference clock
0	Select SOSC as DSWDT reference clock

Bits 25:21 – DSWDTPS[4:0] Deep Sleep Watchdog Timer Postscale Select

The DS WDT prescaler is 32; this creates an approximate base time unit of 1 ms.

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
11111	1:2³⁶ (25.7 days)
11110	1:2³⁵ (12.8 days)
11101	1:2³⁴ (6.4 days)
11100	1:2³³ (77.0 hours)
11011	1:2³² (38.5 hours)
11010	1:2³¹ (19.2 hours)
11001	1:2³⁰ (9.6 hours)
11000	1:2²⁹ (4.8 hours)
10111	1:2²⁸ (2.4 hours)
10110	1:2²⁷ (72.2 minutes)
10101	1:2²⁶ (36.1 minutes)
10100	1:2²⁵ (18.0 minutes)
10011	1:2²⁴ (9.0 minutes)
10010	1:2²³ (4.5 minutes)
10001	1:2²² (135.3 s)
10000	1:2²¹ (67.7 s)
01111	1:2²⁰ (33.825 s)
01110	1:2¹⁹ (16.912 s)
01101	1:2¹⁸ (8.456 s)
01100	1:2¹⁷ (4.228 s)
01011	1:65536 (2.114 s)
01010	1:32768 (1.057 s)
01001	1:16384 (528.5 ms)
01000	1:8192 (264.3 ms)
00111	1:4096 (132.1 ms)
00110	1:2048 (66.1 ms)
00101	1:1024 (33 ms)
00100	1:512 (16.5 ms)
00011	1:256 (8.3 ms)
00010	1:128 (4.1 ms)
00001	1:64 (2.1 ms)
00000	1:32 (1 ms)

Bit 20 – DSZPBOREN Deep Sleep Zero-Power BOR Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	ZPBOR during deep sleep is enabled
0	ZPBOR during deep sleep is disabled

Bits 19:17 – CPEN_DLY[2:0] Charge-pump Ready Digital Delay (Safety delay to Analog CP Ready)

n = (n+1) LPRC Clock Cycle Delay

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.

Bit 16 – RTCEVTYPE RTCC Event Type

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	RTC_EVENT
0	RTC_OUT

Bit 15 – MLPCLK_MOD LPCLK Modifier in Counter/Delay Mode

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Divide-by 1.024 (Recommended, when LPCLK = 32.768 KHz)
0	Divide-by 1 (Recommended, when LPCLK = 32 KHz)

Bit 14 – VBKP_DIVSEL VDDBUKPCORE LPCLK Clock Divider Selection

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Divide by 31.25 (Recommended, when LPCLK = 32 KHz)
0	Divide-by 32 (Recommended, when LPCLK = 32.768 KHz)

Bits 13:12 – VBKP_32KCSEL[1:0] VDDBUKPCORE 32 KHz Clock Source Selection

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
11	LPRC
10	SOSC
01	POSC
00	FRC

Bit 11 – VBKP_1KCSEL VDDBUKPCORE LPCLK Clock Selection

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	Divide by 32 or 31.25 clock depending on VBKP_DIVSEL
0	32 KHz low power clock

Bit 10 – RTCEVENT_EN Output Enable for RTCC Event Output

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
1	RTCC-Event output is enabled
0	RTCC-Event output is disabled

Bits 9:8 – RTCEVENTSEL[1:0] RTCC Event Selection

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.

Value	Description
00	1-Second clock
01	Alarm pulse
1x	32 KHz clock

Bits 7:0 – SOSC_CFG[7:0] SOSC Configuration Bits

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.