10.1.3.1 MATRIX Configuration for MPDDRC Single Port Setting (Default)
The default configuration is single port, with all devices accessed on D0-D15: SDRAM and/or NAND Flash and/or SMC. This configuration is the Reset state SFR_CCFG_EBICSA.DDR_MP_EN = 0.
As the DDRC multiport feature is disabled, all hosts access DDR-SDRAM using MATRIX Client 1 (MPDDRC port 0), sharing it with EBI accesses.
The NAND Flash can be located either on D0-D7 or on D16-D23 depending on SFR_CCFG_EBICSA.NFD0_ON_D16, respectively 0 (default) or 1.
| Hosts | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Clients | ISC DMA | XLCDC DMA | GMAC DMA | XDMAC IF0 | XDMAC IF1 | GFX2D | SDMMC0 DMA | SDMMC1 DMA | UDPHS DMA | UHPHS EHCI | UHPHS OHCI | Reserved | Arm926 Instruc. | Arm926 Data | |
| 0 | MPDDRC port 4 | – | – | – | – | – | – | – | – | – | – | – | – | – | – |
| 1 | EBI (NAND Flash, SMC) | – | – | – | ✓ | ✓ | – | – | – | – | – | – | – | ✓ | ✓ |
| MPDDRC port 0 | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | – | ✓ | ✓ | |
| 2 | MPDDRC port 1 | – | – | – | – | – | – | – | – | – | – | – | – | – | – |
| 3 | MPDDRC port 2 | – | – | – | – | – | – | – | – | – | – | – | – | – | – |
| 4 | MPDDRC port 3 | – | – | – | – | – | – | – | – | – | – | – | – | – | – |
| 5 | SRAM0 | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | – | ✓ | ✓ |
| 6 | OTPC client I/F | – | – | – | ✓ | ✓ | – | – | – | ✓ | – | – | – | ✓ | ✓ |
| 7 | CSI2DC | – | – | – | ✓ | – | – | – | – | – | – | – | – | – | ✓ |
| 8 | APB0 | – | – | – | ✓ | ✓ | – | – | – | – | – | – | – | – | ✓ |
| 9 | APB1 | – | – | – | ✓ | ✓ | – | – | – | – | – | – | – | – | ✓ |
| 10 | QSPI | – | ✓ | – | ✓ | ✓ | – | – | – | – | – | – | – | ✓ | ✓ |
| 11 | UDPHS DPRAM | – | – | – | – | – | – | – | – | – | – | – | – | ✓ | ✓ |
| UHPHS EHCI config. register | |||||||||||||||
| UHPHS OHCI config. reg. | |||||||||||||||
| SDMMC0 config. reg. | |||||||||||||||
| SDMMC1 config. reg. | |||||||||||||||
| SRAM1 Port 1 | |||||||||||||||