10.1.3.2 MATRIX Configuration for MPDDRC Multiport Setting
If the NAND Flash is located on D16-D23, the MPDDRC multiport feature can be enabled. The NAND Flash has its own dedicated port (Client 1) and other peripherals are distributed across four other MATRIX clients (0, 2, 3 and 4), respectively on DDR ports 4, 1, 2 and 3.
This configuration is achieved by setting the bits SFR_CCFG_EBICSA.NFD0_ON_D16 and SFR_CCFG_EBICSA.DDR_MP_EN.
By default, the round-robin arbitration scheme is enabled in MPDDRC. If the system is latency-sensitive, the quality of service (QoS) policy can be enabled in MPDDRC by setting MPDDRC_CONF_ARBITER.ARB to 3.
| Hosts | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Clients | ISC DMA | XLCDC DMA | GMAC DMA | XDMAC IF0 | XDMAC IF1 | GFX2D | SDMMC0 DMA | SDMMC1 DMA | UDPHS DMA | UHPHS EHCI | UHPHS OHCI | Reserved | Arm926 Instruc. | Arm926 Data | |
| 0 | MPDDRC port 4 | ✓ | ✓ | ✓ | – | – | – | – | – | – | – | – | – | – | – |
| 1 | NAND Flash | – | – | – | ✓ | ✓ | – | – | – | – | – | – | – | ✓ | ✓ |
| MPDDRC port 0 | – | – | – | – | – | – | – | – | – | – | – | – | – | – | |
| 2 | MPDDRC port 1 | – | – | – | ✓ | – | – | ✓ | – | – | – | – | – | ✓ | – |
| 3 | MPDDRC port 2 | – | – | – | – | ✓ | ✓ | – | ✓ | – | – | – | – | – | ✓ |
| 4 | MPDDRC port 3 | – | – | – | – | – | – | – | – | ✓ | ✓ | ✓ | – | – | – |
| 5-11 | No change | ||||||||||||||