10.1.3.3 MATRIX Alternate Configurations
If the NAND Flash is located on D16-D23 (SFR_CCFG_EBICSA.NFD0_ON_D16 = 1) and more flexibility is required, an alternate configuration can be achieved with one bit per host to control port distribution.
Configure MPDDRC in single port (SFR_CCFG_EBICSA.DDR_MP_EN = 0) and remap individual ports via the Remap Multiport DDR register (SFR_REMAP_MP_DDR).
Configuration Example
When SFR_REMAP_MP_DDR = 14’b11111111011111, all hosts have a multiport MATRIX client configuration except GFX2D (Host_5), which keeps the single port MATRIX client configuration (MATRIX Client 1).
Performance is increased, since GFX2D uses MATRIX Client 1 (used only for NAND Flash in this configuration), avoiding an arbitration stage with Arm926 data on MATRIX Client 3.
| Hosts | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Clients | ISC DMA | XLCDC DMA | GMAC DMA | XDMAC0 | XDMAC1 | GFX2D | SDMMC0 DMA | SDMMC1 DMA | UDPHS DMA | UHPHS EHCI | UHPHS OHCI | Reserved | Arm926 Instruc. | Arm926 Data | |
| 0 | MPDDRC port 4 | ✓ | ✓ | ✓ | – | – | – | – | – | – | – | – | – | – | – |
| 1 | NAND Flash | – | – | – | ✓ | ✓ | – | – | – | – | – | – | – | ✓ | ✓ |
| MPDDRC port 0 | – | – | – | – | – | ✓ | – | – | – | – | – | – | – | – | |
| 2 | MPDDRC port 1 | – | – | – | ✓ | – | – | ✓ | – | – | – | – | – | ✓ | – |
| 3 | MPDDRC port 2 | – | – | – | – | ✓ | – | – | ✓ | – | – | – | – | – | ✓ |
| 4 | MPDDRC port 3 | – | – | – | – | – | – | – | – | ✓ | ✓ | ✓ | – | – | – |
| 5-11 | No change | ||||||||||||||