26.5.3 Master Control A
| Name: | MCTRLA |
| Offset: | 0x03 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RIEN | WIEN | QCEN | TIMEOUT[1:0] | SMEN | ENABLE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 7 – RIEN Read Interrupt Enable
Writing this bit to '1' enables interrupt on the Master Read Interrupt Flag (RIF) in the Master Status register (TWI.MSTATUS). A TWI Master read interrupt would be generated only if this bit, the RIF, and the Global Interrupt Flag (I) in CPU.SREG are all '1'.
Bit 6 – WIEN Write Interrupt Enable
Writing this bit to '1' enables interrupt on the Master Write Interrupt Flag (WIF) in the Master Status register (TWI.MSTATUS). A TWI Master write interrupt will be generated only if this bit, the WIF, and the Global Interrupt Flag (I) in CPU.SREG are all '1'.
Bit 4 – QCEN Quick Command Enable
Writing this bit to '1' enables Quick Command. When Quick Command is enabled, the corresponding interrupt flag is set immediately after the slave acknowledges the address. At this point the software can either issue a Stop command or a repeated Start by writing either the Command bits (CMD) in the Master Control B register (TWI.MCTRLB) or the Master Address register (TWI.MADDR).
Bits 3:2 – TIMEOUT[1:0] Inactive Bus Timeout
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLED | Bus timeout disabled. I2C. |
| 0x1 | 50US | 50µs - SMBus (assume baud is set to 100kHz) |
| 0x2 | 100US | 100µs (assume baud is set to 100kHz) |
| 0x3 | 200US | 200µs (assume baud is set to 100kHz) |
Bit 1 – SMEN Smart Mode Enable
Writing this bit to '1' enables the Master smart mode. When smart mode is enabled, the acknowledge action is sent immediately after reading the Master Data (TWI.MDATA) register.
Bit 0 – ENABLE Enable TWI Master
Writing this bit to '1' enables the TWI as Master.