26.5.4 Master Control B

Name: MCTRLB
Offset: 0x04
Reset: 0x00
Property: -

Bit 76543210 
     FLUSHACKACTCMD[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 3 – FLUSH Flush

Writing a '1' to this bit generates a strobe for one clock cycle disabling and then enabling the master.

Writing '0' has no effect.

The purpose is to clear the internal state of master: For TWI master to transmit successfully, it is recommended to write the Master Address register (TWI.MADDR) first and then the Master Data register (TWI.MDATA).

The peripheral will transmit invalid data if TWI.MDATA is written before TWI.MADDR. To avoid this invalid transmission, write '1' to this bit to clear both registers.

Bit 2 – ACKACT Acknowledge Action

This bit defines the master’s behavior under certain conditions defined by the bus protocol state and software interaction. The acknowledge action is performed when DATA is read, or when an execute command is written to the CMD bits.

The ACKACT bit is not a flag or strobe, but an ordinary read/write accessible register bit. The default ACKACT for master read interrupt is “Send ACK” (0). For master write, the code will know that no acknowledge should be sent since it is itself sending data.

ValueDescription
0 Send ACK
1 Send NACK

Bits 1:0 – CMD[1:0] Command

The master command bits are strobes. These bits are always read as zero.

Writing to these bits triggers a master operation as defined by the table below.

Table 26-4. Command Settings
CMD[1:0] DIR Description
0x0 X NOACT
0x1 X REPSTART - Execute Acknowledge Action succeeded by repeated Start.
0x2 0 RECVTRANS - Execute Acknowledge Action succeeded by a byte read operation.
1 Execute Acknowledge Action (no action) succeeded by a byte send operation.(1)
0x3 X STOP - Execute Acknowledge Action succeeded by issuing a STOP condition.
Note:
  1. For a master being a sender, it will normally wait for new data written to the Master Data Register (TWI.MDATA).
The acknowledge action bits and command bits can be written at the same time.