33.5.14 Negative Input Multiplexer

Name:	MUXNEG
Offset:	0x0D
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
	VIA[1:0]		MUXNEG[5:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:6 – VIA[1:0]

This bit field controls how the analog input is connected to the ADC input.

Note: The VIA bits in MUXPOS and MUXNEG are shared, so a value written to the VIA bit field in one of the two registers is updated in both. It is, therefore, not possible to have one input using the PGA and the other not using the PGA.

Value	Name	Description
0x0	DIRECT	Input connected directly to the ADC
0x1	PGA	Input connected to the ADC via the PGA
Other	-	Reserved

Bits 5:0 – MUXNEG[5:0] Negative Input Multiplexer

This bit field controls which analog input is connected to the negative input of the ADC/PGA. Changing this setting may require some settling time. Refer to the Electrical Characteristics section for further details.


Value	Name	Description
`0x00`	`AIN0`	Negative pin 0
`0x01`	`AIN1`	Negative pin 1
`0x02`	`AIN2`	Negative pin 2
`0x03`	`AIN3`	Negative pin 3
`0x04`	`AIN4`	Negative pin 4
`0x05`	`AIN5`	Negative pin 5
`0x06`	`AIN6`	Negative pin 6
`0x07`	`AIN7`	Negative pin 7
`0x10`	`AIN16`	Negative pin 16
`0x11`	`AIN17`	Negative pin 17
`0x12`	`AIN18`	Negative pin 18
`0x13`	`AIN19`	Negative pin 19
`0x14`	`AIN20`	Negative pin 20
`0x15`	`AIN21`	Negative pin 21
`0x16`	`AIN22`	Negative pin 22
`0x17`	`AIN23`	Negative pin 23
`0x18`	`AIN24`	Negative pin 24
`0x19`	`AIN25`	Negative pin 25
`0x1A`	`AIN26`	Negative pin 26
`0x1B`	`AIN27`	Negative pin 27
`0x1C`	`AIN28`	Negative pin 28
`0x1D`	`AIN29`	Negative pin 29
`0x1E`	`AIN30`	Negative pin 30
`0x1F`	`AIN31`	Negative pin 31
`0x30`	`GND`	Ground
`0x39`	`DACREF0`	AC0 DAC Voltage Reference
`0x3A`	`DACREF1`	AC1 DAC Voltage Reference
`Other`	-	Reserved