33.5.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | LOWLAT | ENABLE | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 7 – RUNSTDBY Run in Standby
This bit controls whether the ADC will run in Standby sleep mode or not.
| Value | Description |
|---|---|
| 0 | The ADC will not run in Standby sleep mode. An ongoing conversion will finish before the ADC enters sleep mode. |
| 1 | The ADC will run in Standby sleep mode. The main clock will be requested when the ADC is triggered to perform a conversion. |
Bit 5 – LOWLAT Low Latency
This bit controls whether the analog modules required by the ADC are enabled continuously or only when needed.
| Value | Description |
|---|---|
| 0 | The ADC enables the required analog modules only when starting a conversion, which reduces the overall power consumption of the ADC and increases the initialization time when starting an ADC conversion. |
| 1 | The
analog modules stay enabled when selected as input to the ADC. Using this
setting will minimize the initialization time of the ADC. Note: LOWLAT does not keep the
clock source enabled when the ADC is not converting, so a clock startup
delay may be experienced even though LOWLAT is set. Be sure that the
clock source is always enabled to avoid a
delay. |
Bit 0 – ENABLE ADC Enable
This bit controls whether the ADC is enabled or not.
| Value | Description |
|---|---|
| 0 | The ADC is disabled |
| 1 | The ADC is enabled |