33.5.13 Positive Input Multiplexer

Name:	MUXPOS
Offset:	0x0C
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
	VIA[1:0]		MUXPOS[5:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:6 – VIA[1:0]

This bit field controls how the analog input is connected to the ADC input.

Note: The VIA bits in MUXPOS and MUXNEG are shared, so a value written to the VIA bit field in one of the two registers is updated in both. It is, therefore, not possible to have one input using the PGA and the other not using the PGA.

Value	Name	Description
0x0	DIRECT	Input connected directly to the ADC
0x1	PGA	Input connected to the ADC via the PGA
Other	-	Reserved

Bits 5:0 – MUXPOS[5:0] Positive Input Multiplexer

This bit field controls which analog input is connected to the positive input of the ADC/PGA. Changing this setting may require some settling time. Refer to the Electrical Characteristics section for further details.


Value	Name	Description
`0x00`	`AIN0`	Positive pin 0
`0x01`	`AIN1`	Positive pin 1
`0x02`	`AIN2`	Positive pin 2
`0x03`	`AIN3`	Positive pin 3
`0x04`	`AIN4`	Positive pin 4
`0x05`	`AIN5`	Positive pin 5
`0x06`	`AIN6`	Positive pin 6
`0x07`	`AIN7`	Positive pin 7
`0x10`	`AIN16`	Positive pin 16
`0x11`	`AIN17`	Positive pin 17
`0x12`	`AIN18`	Positive pin 18
`0x13`	`AIN19`	Positive pin 19
`0x14`	`AIN20`	Positive pin 20
`0x15`	`AIN21`	Positive pin 21
`0x16`	`AIN22`	Positive pin 22
`0x17`	`AIN23`	Positive pin 23
`0x18`	`AIN24`	Positive pin 24
`0x19`	`AIN25`	Positive pin 25
`0x1A`	`AIN26`	Positive pin 26
`0x1B`	`AIN27`	Positive pin 27
`0x1C`	`AIN28`	Positive pin 28
`0x1D`	`AIN29`	Positive pin 29
`0x1E`	`AIN30`	Positive pin 30
`0x1F`	`AIN31`	Positive pin 31
`0x30`	`GND`	Ground
`0x31`	`VDDDIV10`	VDD divided by 10
`0x32`	`TEMPSENSE`	Temperature sensor
`Other`	-	Reserved