23.5.17 Offset Register
The TCEn.OFFSETL and TCEn.OFFSETH register pair represents the 16-bit value,
TCEn.OFFSET. The low byte [7:0] (suffix L) is accessible at the
original offset. The high byte [15:8] (suffix H) can be accessed at offset +
0x01. CPU and UPDI write access has priority over internal updates of the register.
The TCEn.OFFSET register holds the 16-bit value to set the offset adjustment for the
compare register. When SCALE and AMPEN in TCEn.CTRLD are enabled, the OFFSET
register is automatically updated after a write to the AMP register, based on the
configuration in SCALEMODE bitfield in TCEn.CTRLD.
| Name: | OFFSET |
| Offset: | 0x24 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | OFFSET[15:8] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | OFFSET[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:8 – OFFSET[15:8] Scale Offset High
Byte
This bit field holds
the MSB of the 16-bit Offset register.
Bits 7:0 – OFFSET[7:0] Scale Offset Low
Byte
This bit field holds the LSB
of the 16-bit Offset register.
