23.5.12 Interrupt Flag Register

Note: Any individual bits can be cleared by writing a ‘1’ to its bit location, allowing each bit to be set without using a Read-Modify-Write operation on a single register.

Name:	INTFLAGS
Offset:	0x0B
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
	CMP3	CMP2	CMP1	CMP0				OVF
Access	R/W	R/W	R/W	R/W				R/W
Reset	0	0	0	0				0

Bits 4, 5, 6, 7 – CMPn Compare Channel n Interrupt Flag

The Compare Interrupt (CMPn) flag is set on a compare match on the corresponding compare channel. For all modes of operation, the CMPn flag will be set when a compare match occurs between the Count (TCEn.CNT) register and the corresponding Compare (TCEn.CMPn) register. The CMPn flag is not cleared automatically, only by writing a ‘1’ to its bit location.

Bit 0 – OVF Overflow/Underflow Interrupt Flag

This flag is set either on a TOP (overflow) or BOTTOM (underflow) condition, depending on the WGMODE setting. The OVF flag is not cleared automatically. It will be cleared only by writing a ‘1’ to its bit location.

Any individual bits can be cleared by writing a ‘1’ to its bit location, allowing each bit to be set without using a Read-Modify-Write operation on a single register.