23.5.2 Control B
| Name: | CTRLB |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMP3EN | CMP2EN | CMP1EN | CMP0EN | ALUPD | WGMODE[2:0] | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 4, 5, 6, 7 – CMPnEN Compare n Enable
| Value | Description |
|---|---|
| 0 | Waveform output WOn will not be available on the corresponding pin |
| 1 | Waveform output WOn will override the output value of the corresponding pin in FRQ and PWM Waveform Generation mode |
Bit 3 – ALUPD Auto-Lock Update
The Auto-Lock Update bit controls the Lock Update (LUPD) bit in the TCEn.CTRLE
register. When writing ALUPD to ‘1’, the LUPD bit will be set
to ‘1’ until the Buffer Valid (CMPnBV) bits of all enabled
compare channels are ‘1’. This condition will clear the LUPD
bit.
It will remain clear until the following UPDATE condition, where
the CMPnBUF registers will be transferred to the CMPn registers, and the LUPD
bit will be set to ‘1’ again, making sure that the CMPnBUF
register values are not transferred to the CMPn registers until all enabled
compare buffers are written.
| Value | Description |
|---|---|
| 0 | LUPD bit in the TCEn.CTRLE register is not altered by the system |
| 1 | LUPD bit in the TCEn.CTRLE register is set and cleared automatically |
Bits 2:0 – WGMODE[2:0] Waveform Generation Mode
This bit field selects the Waveform Generation mode and controls the counting sequence of the counter, TOP value, UPDATE condition, interrupt condition, and the type of waveform generated.
No waveform generation is performed in the Normal mode of operation. For all other modes, the waveform generator output will only be directed to the port pins if the corresponding CMPnEN bit has been set. The port pin direction must be set as output.
| Value | Name | Description |
|---|---|---|
| 0x0 | NORMAL | Normal operation mode |
| 0x1 | FRQ | Frequency mode |
| 0x2 | - | Reserved |
| 0x3 | SINGLESLOPE | Single-Slope PWM mode |
| 0x4 | - | Reserved |
| 0x5 | DSTOP | Dual-Slope PWM mode with overflow on TOP |
| 0x6 | DSBOTH | Dual-Slope PWM mode with overflow on TOP and BOTTOM |
| 0x7 | DSBOTTOM | Dual-Slope PWM mode with overflow on BOTTOM |