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SmartTime Static Timing Analyzer (STA) User Guide Libero® SoC v2022.2
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11
SmartTime Dialog Boxes
11.2
Analysis Set Properties Dialog Box
11.2.3
Creation Filter
Libero® SoC v2022.2
Introduction
1
About SmartTime
2
Design Flows with SmartTime
3
Starting and Closing SmartTime
4
Configuring SmartTime Settings
5
SmartTime Toolbar
6
SmartTime Timing Analyzer
7
Advanced Timing Analysis
8
Generating Timing Reports
9
Timing Concepts
10
SmartTime Tutorials
11
SmartTime Dialog Boxes
11.1
Add Path Analysis Set Dialog Box
11.2
Analysis Set Properties Dialog Box
11.2.1
Name
11.2.2
Parent Set
11.2.3
Creation Filter
11.2.4
To
11.3
Edit Filter Set Dialog Box
11.4
Customize Analysis View Dialog Box
11.5
Manage Clock Domains Dialog Box
11.6
Set False Path Constraint Dialog Box
11.7
SmartTime Options Dialog Box
11.8
Create Filter Set Dialog Box
11.9
Timing Bottleneck Analysis Options Dialog Box
11.10
Timing Datasheet Report Options Dialog Box
11.11
Timing Report Options Dialog Box
11.12
Timing Violations Report Options Dialog Box
11.13
Data Change History - SmartTime
12
Tcl Commands
13
Glossary
14
Revision History
Microchip FPGA Support
Microchip Information
11.2.3 Creation Filter
Specifies a list of source pins in the user-created path set.
