24.5.1 PMD1 - Peripheral Module Disable 1 Register

Note: This register's bits are only writable when CFGCON0.PMDLOCK = 0.
Name: PMD1
Offset: 0x00E0
Reset: 0x00000000
Property: -

Bit 3130292827262524 
   QSPIMD      
Access R/W/L 
Reset 0 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
      ADCSAR-SHRMDCVDMDADCSARMD 
Access R/W/LR/W/LR/W/L 
Reset 000 
Bit 76543210 
 ADCMDACMDDACMD      
Access R/W/LR/W/LR/W/L 
Reset 000 

Bit 29 – QSPIMD SPI Module Disable

Note: This bit is only writable when CFGCON0.PMDLOCK = 0
ValueDescription
1Disables the SPI module
0Enables the SPI module

Bit 10 – ADCSAR-SHRMD Shared ADC SAR Core Module Disable bit

Note: This bit is only writable when CFGCON0.PMDLOCK = 0
ValueDescription
1Disables the shared ADC SAR core module
0Enables the shared ADC SAR core module

Bit 9 – CVDMD Shared CVD Module Disable Bit

ValueDescription
1Disables the corresponding shared CVD module
0Enables the corresponding shared CVD module

Bit 8 – ADCSARMD Shared ADC SAR Core Module Disable Bit

ValueDescription
1Disables the shared ADC SAR Core module
0Enables the shared ADC SAR Core module

Bit 7 – ADCMD ADC Controller Module Disable

ValueDescription
1Disables the ADC Controller module
0Enables the ADC Controller module

Bit 6 – ACMD AC Module Disable

ValueDescription
1Disables the AC module
0Enables the AC module

Bit 5 – DACMD DAC Module Disable

Note: This bit is only writable when CFGCON0.PMDLOCK = 0
ValueDescription
1 Disables the DAC module
0 Enables the DAC module