24.5.2 PMD2 - Peripheral Module Disable 2 Register
Note: This register bits are only
writable when CFGCON0.PMDLOCK =
0. | Name: | PMD2 |
| Offset: | 0x00F0 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| REFO4MD | REFO3MD | REFO2MD | REFO1MD | REFO6MD | REFO5MD | ||||
| Access | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 31 – REFO4MD Reference (Clock) Out 4 Disable
| Value | Description |
|---|---|
| 1 | Disables the Reference (clock) out 4 |
| 0 | Enables the Reference (clock) out 4 |
Bit 30 – REFO3MD Reference (Clock) Out 3 Disable
| Value | Description |
|---|---|
| 1 | Disables the Reference (clock) out 3 |
| 0 | Enables the Reference (clock) out 3 |
Bit 29 – REFO2MD Reference (Clock) Out 2 Disable
| Value | Description |
|---|---|
| 1 | Disables the Reference (clock) out 2 |
| 0 | Enables the Reference (clock) out 2 |
Bit 28 – REFO1MD Reference (Clock) Out 1 Disable
| Value | Description |
|---|---|
| 1 | Disables the Reference (clock) out 1 |
| 0 | Enables the Reference (clock) out 1 |
Bit 25 – REFO6MD Reference (Clock) Out 6 Disable
| Value | Description |
|---|---|
| 1 | Disables the Reference (clock) out 6 |
| 0 | Enables the Reference (clock) out 6 |
Bit 24 – REFO5MD Reference (Clock) Out 5 Disable
| Value | Description |
|---|---|
| 1 | Disables the Reference (clock) out 5 |
| 0 | Enables the Reference (clock) out 5 |