8.2.1 System Power-Up

At power-up, from a power supply sequencing perspective, the SAMA7D65 SOM Series power supplies are categorized into eight independent groups:

5V_MAIN (main supply)
VBAT (backup supply)
VDD_3V3 (internal periphery group) containing VDDIN33, VDDQSPI0, VDDSDMMC0 and VDDGMAC0 inputs
VDD_1V1_ETH supply (internal Ethernet core group)
External VDD_PERIPH (external periphery group) containing VDDGMAC1, VDDSDMMC1, VDDSDMMC2, VDDIOP0 and VDDIOP1 inputs
VDDLVDS and VDDMIPI supplies (video group)
VDDIODDR supply (memory group)
VDDCORE and VDDCPU supplies (core group)

Figure 8-2 shows the recommended power-up sequence.

Note:

VBAT
- When supplied from a precharged storage element (battery, supercapacitor or micro-battery), VBAT is an always-on supply input and is therefore not part of the power supply sequencing.
- When no storage element is used on VBAT in the application, VBAT must be tied to VDD_3V3.
- When a supercapacitor or a micro-battery is used in the application to power VBAT in Backup mode, this element must be isolated from VBAT during its (slow) charge, so that VBAT closely follows VDD_3V3. In Table 8-2, the parameter t₁ limits the delay to establish VBAT after VDD_3V3.
VDD_2V5 is the output of the internal 2.5V regulator; therefore, there is no power supply requirement on this pin.

Figure 8-2. Recommended Power-Up Sequence

Note:

VDD_3V3 is generated internally by the MCP16502 PMIC and directly supplies the internal periphery group.
VDDIODDR is generated internally by the MCP16502 PMIC and directly supplies the memory group.
This group is supplied externally and requires no specific order. Only timing t₃ must be respected.
VDD_1V1_ETH is generated internally by the MIC33153 and directly supplies the internal Ethernet core group.
VDD_2V5 is generated internally by the SAMA7D65 SiP device and can be used to directly supply the internal video group.
VLDO1 is started at the same time as VDD_3V3. It is the default state at the first start-up. The VLDO1 “On” condition can be changed by the I²C interface.
VDDCORE and VDDCPU are generated internally by the MCP16502 PMIC and directly supplies the core and cpu groups.
The RESET general signal is generated internally by the MCP16502 PMIC and distributed throughout the whole system.

Table 8-2. Power-Up Timing Requirements
Symbol	Parameter	Conditions⁽¹⁾	Min	Typ⁽²⁾	Max	Unit
t₀	nSTART_SOM deglitch time	From nSTART_SOM pin falling edge	–	0.5	–	ms
t₁	VBAT delay	Delay from established VDD_3V3 to established VDDBU	–	–	0.2	ms
t₂	VDD_3V3 to Memory group delay	Delay from established VDD_3V3 to the VDDIODDR supply turn-on	–	8	–	ms
t₃	VDD_3V3 to External Periphery group delay ⁽³⁾	Delay from established VDD_3V3 to the external periphery group established supply	0	–	t₂	ms
t₄	Periphery group to VDDCORE, VDDCPU delay	Delay from the periphery group established supply to the VDDCORE, VDDCPU supplies turn-on	–	4	–	ms
t₅	Reset delay at power-up	From established VDDCORE to NRST high	–	16	–	ms

Note:

The term "established" refers to a power supply having reached 90% of its final value.
Typical timing values can be programmed in MCP16502 PMIC registers (RSTDLY[2:0]), but they must follow the timing sequence required by the SAMA7D65 SiP device.
If one of the power inputs of the group is supplied externally, the power must be applied at the same time or after the presence of VDD_3V3 and before the presence of VDDIODDR.