8.2.2 System Power-Down

The following figure shows the SAMA7D65 SOM Series power-down sequence that starts by asserting the SHDN line to "0".

Once SHDN and NRST are asserted, the supply inputs can be immediately shut down without any specific timing or order. VBAT may not be shut down if the application uses a backup storage element on this supply input.

Figure 8-3. Recommended Power-Down Sequence
Note:
  1. SHDN is generated internally by a software request from the SAMA7D65 SiP device.
  2. All these signals and power rails are controlled internally by the MCP16502 PMIC and are switched off at the same time.
  3. This group is supplied externally and there is no order required on this supply group. Only timing t3 must be respected.
  4. VDDLVDS is automatically switched off, as described in the above figure, if it is connected to VDD_2V5.
Table 8-3. Power-Down Timing Requirements
SymbolParameterConditionsMinTypMaxUnit
t1SHDN to NRST delay at power-downDelay from SHDN asserted to NRST generation0–50µs
t2NRST delay at power-downDelay from NRST asserted to first supply turn-off0–10µs
t3External supply delay at power-downDelay from NRST asserted to external supplies turn-offt2–1ms