5.1 Supply Pins
(Ask a Question)| Name | Type | Description |
|---|---|---|
| GND | Ground | Digital ground to the FPGA fabric, microcontroller subsystem and GPIOs |
| GND15ADC0 | Ground | Quiet analog ground to the 1.5V circuitry of the first analog-to-digital converter (ADC) |
| GND15ADC1 | Ground | Quiet analog ground to the 1.5V circuitry of the second ADC |
| GND15ADC2 | Ground | Quite analog ground to the 1.5V circuitry of the third ADC |
| GND33ADC0 | Ground | Quiet analog ground to the 3.3V circuitry of the first ADC |
| GND33ADC1 | Ground | Quiet analog ground to the 3.3V circuitry of the second ADC |
| GND33ADC2 | Ground | Quiet analog ground to the 3.3V circuitry of the third ADC |
| GNDA | Ground | Quiet analog ground to the analog front-end |
| GNDAQ | Ground | Quiet analog ground to the analog I/O of SmartFusion cSoCs |
| GNDENVM | Ground | Digital ground to the embedded nonvolatile memory (eNVM) |
| GNDLPXTAL | Ground | Analog ground to the low power 32 KHz crystal oscillator circuitry |
| GNDMAINXTAL | Ground | Analog ground to the main crystal oscillator circuitry |
| GNDQ | Ground | Quiet digital ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise originated from the output buffer ground domain. This minimizes the noise transfer within the package and improves input signal integrity. GNDQ needs to always be connected on the board to GND. |
| GNDRCOSC | Ground | Analog ground to the integrated RC oscillator circuit |
| GNDSDD0 | Ground | Analog ground to the first sigma-delta DAC |
| GNDSDD1 | Ground | Common analog ground to the second and third sigma-delta DACs |
| GNDTM0 | Ground | Analog temperature monitor common ground for signal conditioning blocks SCB 0 and SCB 1 (see information for pins TM0 and TM1 in the 5.8 Analog Front-End (AFE) section). |
| GNDTM1 | Ground | Analog temperature monitor common ground for signal conditioning block SCB 2 and SBCB 3 (see information for pins TM2 and TM3 in the 5.8 Analog Front-End (AFE) section). |
| GNDTM2 | Ground | Analog temperature monitor common ground for signal conditioning block SCB4 |
| GNDVAREF | Ground | Analog ground reference used by the ADC. This pad should be connected to a quiet analog ground. |
| VCC | Supply | Digital supply to the FPGA fabric and MSS, nominally 1.5V. VCC is also required for powering the JTAG state machine, in addition to VJTAG. Even when a SmartFusion cSoC is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass through the SmartFusion cSoC. |
| VCC15A | Supply | Clean analog 1.5V supply to the analog circuitry. Always power this pin. |
| VCC15ADC0 | Supply | Analog 1.5V supply to the first ADC. Always power this pin. |
| VCC15ADC1 | Supply | Analog 1.5V supply to the second ADC. Always power this pin. |
| VCC15ADC2 | Supply | Analog 1.5V supply to the third ADC. Always power this pin. |
| VCC33A | Supply | Clean 3.3V analog supply to the analog circuitry. VCC33A is also used to feed the 1.5V voltage regulator for designs that do not provide an external supply to VCC. Refer to the Voltage Regulator (VR), Power Supply Monitor (PSM), and Power Modes section in the SmartFusion Microcontroller Subsystem User’s Guide for more information. |
| VCC33ADC0 | Supply | Analog 3.3V supply to the first ADC. Never ground this pin. Can be left floating if unused.1 |
| VCC33ADC1 | Supply | Analog 3.3V supply to the second ADC. Never ground this pin. Can be left floating if unused.1 |
| VCC33ADC2 | Supply | Analog 3.3V supply to the third ADC. Never ground this pin. Can be left floating if unused.1 |
| VCC33AP | Supply | Analog clean 3.3V supply to the charge pump. To avoid high current draw, VCC33AP should be powered up simultaneously with or after VCC33A. Can be pulled down if unused.1 |
| VCC33N | Supply | –3.3V output from the voltage converter. A 2.2 μF capacitor must be connected from this pin to GND. Analog charge pump capacitors are not needed if none of the analog SCB features are used and none of the SDDs are used. In that case it should be left unconnected. |
| VCC33SDD0 | Supply | Analog 3.3V supply to the first sigma-delta DAC |
| VCC33SDD1 | Supply | Common analog 3.3V supply to the second and third sigma-delta DACs |
| VCCENVM | Supply | Digital 1.5V power supply to the embedded nonvolatile memory blocks. To avoid high current draw, VCC should be powered up before or simultaneously with VCCENVM. |
| VCCESRAM | Supply | Digital 1.5V power supply to the embedded SRAM blocks. Available only on the 208PQFP package. It should be connected to VCC (in other packages, it is internally connected to VCC). |
| VCCFPGAIOB0 | Supply | Digital supply to the FPGA fabric I/O bank 0 (north FPGA I/O bank) for the output buffers and I/O logic. Each bank can have a separate VCCFPGAIO connection. All I/Os in a bank will run off the same VCCFPGAIO supply. VCCFPGAIO can be 1.5V, 1.8V, 2.5V, or 3.3V, nominal voltage. Unused I/O banks should have their corresponding VCCFPGAIO pins tied to GND. |
| VCCFPGAIOB1 | Supply | Digital supply to the FPGA fabric I/O bank 1 (east FPGA I/O bank) for the output buffers and I/O logic. Each bank can have a separate VCCFPGAIO connection. All I/Os in a bank will run off the same VCCFPGAIO supply. VCCFPGAIO can be 1.5V, 1.8V, 2.5V, or 3.3V, nominal voltage. Unused I/O banks should have their corresponding VCCFPGAIO pins tied to GND. |
| VCCFPGAIOB5 | Supply | Digital supply to the FPGA fabric I/O bank 5 (west FPGA I/O bank) for the output buffers and I/O logic. Each bank can have a separate VCCFPGAIO connection. All I/Os in a bank will run off the same VCCFPGAIO supply. VCCFPGAIO can be 1.5V, 1.8V, 2.5V, or 3.3V, nominal voltage. Unused I/O banks should have their corresponding VCCFPGAIO pins tied to GND. |
| VCCLPXTAL | Supply | Analog supply to the low power 32 KHz crystal oscillator. Always power this pin.1 |
| VCCMAINXTAL | Supply | Analog supply to the main crystal oscillator circuit. Always power this pin.1 |
| VCCMSSIOB2 | Supply | Supply voltage to the microcontroller subsystem I/O bank 2 (east MSS I/O bank) for the output buffers and I/O logic. Each bank can have a separate VCCMSSIO connection. All I/Os in a bank will run off the same VCCMSSIO supply. VCCMSSIO can be 1.5V, 1.8V, 2.5V, or 3.3V, nominal voltage. Unused I/O banks should have their corresponding VCCMSSIO pins tied to GND. |
| VCCMSSIOB4 | Supply | Supply voltage to the microcontroller subsystem I/O bank 4 (west MSS I/O bank) for the output buffers and I/O logic. Each bank can have a separate VCCMSSIO connection. All I/Os in a bank will run off the same VCCMSSIO supply. VCCMSSIO can be 1.5V, 1.8V, 2.5V, or 3.3V, nominal voltage. Unused I/O banks should have their corresponding VCCMSSIO pins tied to GND. |
| VCCPLLx | Supply | Analog 1.5V supply to the PLL. Always power this pin. |
| VCCRCOSC | Supply | Analog supply to the integrated RC oscillator circuit. Always power this pin.1 |
| VCOMPLAx | Supply | Analog ground for the PLL |
| VDDBAT | Supply | External battery connection to the low power 32 KHz crystal oscillator (along with VCCLPXTAL), RTC, and battery switchover circuit. Can be pulled down if unused. |
| VJTAG | Supply | Digital supply to the JTAG controller SmartFusion cSoCs have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5V to 3.3V (nominal). Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned to be used, the VJTAG pin together with the TRSTB pin could be tied to GND. Note that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a SmartFusion cSoC is in a JTAG chain of interconnected boards and it is desired to power down the board containing the device, this can be done provided both VJTAG and VCC to the device remain powered; otherwise, JTAG signals will not be able to transition the device, even in bypass mode. See 5.6 JTAG Pins. |
| VPP | Supply | Digital programming circuitry supply SmartFusion cSoCs support single-voltage in-system programming (ISP) of the configuration flash, embedded FlashROM (eFROM), and embedded nonvolatile memory (eNVM). For programming, VPP should be in the 3.3V ± 5% range. During normal device operation, VPP can be left floating or can be tied to any voltage between 0V and 3.6V. When the VPP pin is tied to ground, it shuts off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. For proper programming, 0.01 μF and 0.33 μF capacitors (both rated at 16V) are to be connected in parallel across VPP and GND, and positioned as close to the FPGA pins as possible. |
- The following 3.3V supplies should be connected together while following proper noise filtering practices: VCC33A, VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL.
- The following 1.5V supplies should be connected together while following proper noise filtering practices: VCC, VCC15A, and VCC15ADCx.